Henrik's Blog

Online 2D transmission line field solver

2026-01-27T00:00:00+02:00

Introduction

I often use online impedance calculator for quick microstrip, stripline and grounded CPW line dimension calculation. However, they often are not quite good enough. For example when microstrip is covered with solder mask its impedance drops due to dielectric of the mask and the mask increases effective permittivity. Most calculators can't give impedance of the line in that case and it can be significant for thin substrates. Another common issue is unusual transmission lines such as asymmetric stripline, embedded microstrip or lines over ground plane cuts (for example cutout under SMD capacitor or resistor pads). Many calculators are also unable to estimate line losses.

At work I usually use 2D transmission line field solver to simulate cross-sections (E.g., Ansys 2D extractor, OpenParEM, and many others), but it's quite lot of effort to open the program, draw the geometry, setup simulation parameters, and then simulate it. User interface of those programs also often leaves a lot to be desired.

I decided to make my own online 2D transmission line field simulator that works entirely in local browser. It's fast to open and transmission lines can be added just by inputting parameters just like with simple impedance calculators. It supports microstrip, stripline, and grounded CPW lines, both single-ended and differential. There's also support for adding solder mask, top-dielectric for embedded microstrip, cutout in ground plane, and metal enclosure around the line. It calculates both dielectric and conductor loss and can export S-parameters. Nice field visualizations are also included.

For surface roughness Gradient model is implemented. It's relatively new surface roughness model that matches very well with measurements. Loss increase from roughness and increase of inductance due to roughness are calculated. The latter can be very important for simulating filters, and I highly recommend reading the gradient model paper for more information. It's very easy to get or estimate the required RMS roughness parameter for PCB copper foils. Djordjevic-Sarkar (Wideband Debye) causal material model can also be enabled to enforce causality for time-domain simulations.

Accuracy

Measured and modeled stripline loss from gradient model paper (left), and same simulation in my simulator (right).

I tested it against few simulations and measurements with good accuracy. Above is example stripline measurement using the surface roughness model compared against the measurement in Gradient model paper (Figure 23 in the paper). The loss of the stripline calculated with my simulator matches very well. Effective permittivity rise due to increased inductance from the roughness is also simulated well. Click here to open these parameters in the simulator.

I have more tests in source code tests folders against various single-ended and differential transmission lines that are tested against other simulators or measurements. Solved characteristic impedances, RLGC parameters, and losses all currently agree well with the reference simulation or measurements.

More detailed computation method description and limitations of the method are in "About" tab of the program.

Conclusion

Click the image above to open the simulator. The source code is available on GitHub.

Online radar image formation simulator

2026-01-05T00:00:00+02:00

Open application

I was making some radar image formation visualizations using Python and thought that it would be nice if it was instead written in Javascript and ran on my browser. That way I could put some real-time visualizations on my blog posts. I don't have much web development experience, so I gave my Python program to Claude AI and asked it to convert it to Javascript and it did okay job. After one day of manual work I think it's working pretty well and I decided to put it up as a separate web application. Click the above image to open it. It was quite fun to be able to focus on content and leave the web frontend part mostly to the AI, I don't think I would have had enough motivation to make this without it.

Synthetic aperture radar autofocus and calibration

2025-10-07T00:00:00+03:00

Introduction

Radar drone. Since the first post I have added a Gopro camera and a second GPS for redundancy.

Earlier this year I made a polarimetric synthetic aperture radar (SAR) mounted on a drone. I have since worked a lot on the software side to improve the image quality and now the same hardware can generate much better quality images. The main contribution of this article is description of a new SAR autofocus algorithm that combines some of the existing SAR autofocus algorithms to make an algorithm that is well-suited for drone mounted SAR. Also antenna pattern normalization and polarimetric calibration suitable for drone mounted SAR with non-linear track is described.

Radar signal

SAR image formation geometry.

While the drone flies along a track, the radar measures the distances and phases of the targets in the antenna beam. Neither azimuth ($\varphi$) nor elevation ($\theta$) angle of a target can be determined from a single measurement, and all targets at the same range will overlap in the measurement. However, by recording many radar measurements from multiple locations, a radar image can be formed.

Magnitude of a single recorded range compressed radar signal.

Depending on the radar parameters and radiated waveform, the signal processing to obtain a range-compressed signal from the raw recorded data might vary. After range compression, however, the image formation process is essentially the same.

Range resolution is the ability to separate two closely spaced targets. Ideally it's calculated as $\Delta r = c/2B$, where $c$ is speed of light, and $B$ is the bandwidth of the radiated waveform. For example, with a 150 MHz bandwidth the range resolution is 1 m. For a linear flight track this is also the image resolution in range direction.

The phase of the received signal depends on the distance to the target. Because the signal travels to the target and back, a distance change equal to half the wavelength causes a full wavelength (360 degrees) shift in the received signal phase. As a function of target distance, the phase can be written as $\varphi = 4\pi d/\lambda$, where $d$ is distance, and $\lambda$ is wavelength. For instance, with 6 GHz RF frequency, a distance change of 25 mm (1 inch) causes 360 degree phase shift.

SAR image formation

SAR image example with one point target. Radar track and target position (left), magnitude of the recorded radar data at each position (middle), and processed SAR image (right). Platform height is 30 m.

Due to the wide antenna beam there are multiple targets in the beam at the same time, but with signal processing it's possible to separate them and generate much higher resolution image.

To convert a set of radar measurements into a radar image, matched filtering can be used. For each pixel in the image grid, generate a reference signal corresponding to what a target at that position would reflect. For each radar measurement, multiply the measured signal with complex conjugate of the reference signal, then sum these products over all measurements. When the measured signal closely matches the reference signal, their product becomes large because the phases align and target is generated at that location in the image. If the phases don't match, the result of the multiplication is a complex number with a random phase, and summing random complex numbers will average out generating a low response and that pixel in the image will have low amplitude.

Assuming the signal is already range compressed and ignoring the amplitude (antenna pattern and loss due to distance can be compensated after image formation), then the reference signal just needs to compensate for the phase.

The image formation can be written as:

$$I = \sum_{p \in \mathcal{P}} \sum_{n=1}^N S_n(d(\mathbf{p},\mathbf{x_n})) \exp \left(j \frac{4\pi}{\lambda} d(\mathbf{p},\mathbf{x_n})\right)$$

$\mathcal{P}$ is the set of pixels in the image, $N$ is the number of radar measurements, $S_n$ is range compressed single channel radar measurement, and $d(\mathbf{p},\mathbf{x_n})$ is the distance to location of pixel $\mathbf{p}$ from radar position at measurement $\mathbf{x_n}$.

Position error

To get a well focused radar image, the phase of the reference signal used in the matched filtering needs to match with the recorded signal. If there is any error in the actual position of the radar during measurement to the position used in image formation, it will cause errors in the image.

Assuming the target is just a single point and ignoring the amplitude, with $\Delta \mathbf{x_n}$ position error on the $n$th measurement, the error in image at the location of the target can be calculated as:

$$I_p = \sum_{n=1}^N S_n(d(\mathbf{p},\mathbf{x_n})) \exp \left(j \frac{4\pi}{\lambda} d(\mathbf{p},\mathbf{x_n} + \Delta\mathbf{x_n})\right) = \sum_{n=1}^N \exp \left(-j \frac{4\pi}{\lambda} d(\mathbf{p},\mathbf{x_n}) + j \varphi_p\right) \exp \left(j \frac{4\pi}{\lambda} (d(\mathbf{p},\mathbf{x_n} + \Delta\mathbf{x_n})\right)\\ = \sum_{n=1}^N \exp \left(-j \frac{4\pi}{\lambda}\left(d(\mathbf{p},\mathbf{x_n}) - d(\mathbf{p},\mathbf{x_n} + \Delta\mathbf{x_n})\right) + j\varphi_p \right) = \sum_{n=1}^N \exp \left(-j \frac{4\pi}{\lambda}\Delta r_{n,p} + j\varphi_p\right) $$

Instead of all phases lining up at the location of the target, there is some phase offset left that depends on how the position error changes the distance. The remaining error $\Delta r_{n,p}$ is the distance error from $n$th radar position to the target location at pixel $p$.

$\varphi_p$ is a constant phase offset from the target. It can be caused by phase change in reflection, small position offset or just phase offset in the radar electronics.

SAR image example with one point target, with and without linear error in radar position. Radar track and target position (left), image processed without position error (middle), and image processed with linear position error (right) causing shift in the image.

SAR track can have any shape, but often it's a straight line. With this simple track it's possible to calculate how some position errors affect the image.

If the distance error $\Delta r_{n,p}$ is constant, then the error is just a constant phase offset which doesn't affect the magnitude of the image at all.

Linear error affects the image by shifting the azimuth positions of the targets in the image. Analysis for it is in many different papers and textbooks, but a good detailed overview can be found in the paper: "Performance Limit of Phase Gradient Autofocus Class Method for Synthetic Aperture Radar" by C. Tu, Z. Dong, A. Yu, Y. Ji, X. Chen and Z. Zhang.

The same scene, but with more complicated position error. Radar track and position error (left), and image processed with position error (right) causing blurring of the target.

More complicated errors can be thought as piecewise linear error, each piece in the position error causes the resulting image to be formed at different location resulting in a blurred image.

Note the scale of the position error that causes the blurring in the simulate image. The maximum error is only 1 cm, but even this small error causes significant loss in the image quality. Since the image formation relies on the phase, position error must be much smaller than wavelength to not cause phase errors during image formation. In this case the simulation uses 6 GHz RF frequency which corresponds to 5 cm wavelength.

Generalized phase gradient autofocus

The idea behind autofocus algorithms is to estimate the error in radar position from the SAR image and radar data. There are many different autofocus algorithms for different applications, but the most widely used SAR autofocus algorithm is phase gradient autofocus (PGA). The generalized version isn't as well known and was published much later, but in my opinion it's easier to understand with backprojection image formation background.

To simplify the notation let's call the terms used for calculating a single pixel $I_p$ in backprojection $\xi_{n,p}$:

$$\xi_{n,p} = S_n(d(\mathbf{p},\mathbf{x_n})) \exp \left(j \frac{4\pi}{\lambda} d(\mathbf{p},\mathbf{x_n})\right)\\ I_p = \sum_{n=1}^N \xi_{n,p}$$

The idea behind phase gradient autofocus is that if we know that a target in the SAR image is a point target, then phase of $\xi_{n,p}$ should be constant. If this is not the case, the position error can be solved from the $\xi_{n,p}$ by finding a phase offset that makes it constant. The phase error can then be converted to distance to find the position error.

$\xi_{n,p}$ is calculated exactly like a pixel in the backprojection image formation but just without summing up the terms.

SAR image with position error (left) and phase of ξ calculated at the target location compared to position error.

Calculating the demodulated target phase ($\xi_{n,p}$) for the previous example scene gives a phase that matches very well with the X-position error that was added to the radar position. Shifting the phase of the input data by negative of the $\xi_{n,p}$ would result in a constant phase, which results in a focused target in the image.

In this case since the target is on X-axis the distance error is very close to the X-axis error, but this is not the case generally if the target is at some other angle. A more general method for solving for the 3D position error from the phase error will be presented later.

Low-pass filtering will improve the phase error estimation when phase error is slowly varying. SAR image with noise and position error (left) and demodulated phase of the target with and without low-pass filtering (right).

Low-pass filtering is used to filter out noise and clutter at the same distance in measurements as the target. Since the target response is a constant it will be preserved as the signal is low-pass filtered, but any noise and other objects that were momentarily at the same distance as the target being considered are filtered out. Low-pass filtering also filters out high frequency position errors if it's too small, so the low-pass window size should be set carefully.

Low-pass filtering operation is often implemented as Fourier transforming the signal, zeroing the high frequency bins, and then inverse Fourier transforming to get the filtered signal.

GPGA algorithm flow-chart. Algorithm is iterated until either phase error is below a threshold or minimum low-pass filter window size is reached.

The complete GPGA algorithm needs few more operations. In general there are many point-like targets in the same image and for the best position error estimation multiple different targets should be used.

We know that for a point target with position error: $\xi_{n,p} = \exp(-j\frac{4\pi}{\lambda}\Delta r_{n,p} + j\varphi_p)$.

The constant phase offset, $\varphi_p$, that is different for each target makes it impossible to just sum different $\xi_{n,p}$ for each target together. There are few different phase estimators for estimating the phase error from set of $\xi_{n,p}$ from many targets (pixels $p$).

One solution is to calculate:

$$g_{n,p} = \xi_{n-1,p}^* \xi_{n,p} = \exp\left(j\frac{4\pi}{\lambda}\Delta r_{n-1,p} - j\varphi_p\right) \exp\left(-j\frac{4\pi}{\lambda}\Delta r_{n,p} + j\varphi_p\right) = \exp\left(-j\frac{4\pi}{\lambda}(\Delta r_{n,p} - \Delta r_{n-1,p})\right)$$

Multiplying complex conjugate of n+1th term with nth term causes the constant phase to cancel out and the result is a difference in phase errors between adjacent positions (phase gradient in the algorithm name). In this forms the $g_{n,p}$ from different targets can be summed, taking the argument of the sum gives the gradient of the phase error, and the phase error can be recovered up to a constant phase offset by calculating a cumulative sum.

$$g_n = \text{Arg} \left(\sum_{p} g_{n,p}\right)$$

In practice the sum should be weighted according to signal-to-clutter ratio in each target response for the optimal estimate and this weighting will be analyzed later. Finally taking cumulative sum of the phase gradient $g_n$ gives estimate for the phase error.

After correcting the image with the solved phase error, the phase error is reduced but might not be completely gone. Decreasing the low pass window size and repeating the process improves the estimate.

3D trajectory estimation

So far only the phase error has been solved. It can be used to correct the SAR image by multiplying the input data with the negative of the phase error. However, the phase error is proportional to distance error from the radar position to the target, and depending on a target's location, the phase error caused by the position error varies. If several targets at different azimuth and elevation angles are visible at the same time, it might not be possible to focus them all at the same time with a single phase-correction term. This is the case when antenna beam is wide, which is precisely the case with my drone mounted SAR.

Example scenario with two targets and 2D position error. Distance errors to the two targets are not equal due to their different azimuth angle. r1' is about equal to r1 due to direction of the position error being mostly perpendicular to target 1, but this is not the case for target 2. There isn't a single phase correction that will focus them both at the same time.

To get all the targets in focus at the same time it's necessary to solve the 3D position error and use the corrected position of the radar during the image formation.

The 3D trajectory estimation is based on paper "An Autofocus Approach for UAV-Based Ultrawideband Ultrawidebeam SAR Data With Frequency-Dependent and 2-D Space-Variant Motion Errors" by Z. Ding et al. The first step is to divide the SAR image into $K$ subimages and then calculate the phase error in each image using PGA or GPGA. The phase error can be turned into a distance error by unwrapping the phase and multiplying by $\lambda/4\pi$. The result is distance error from each radar position ($N$ positions) to each subimage ($K$ subimages).

GPGA can solve for distance error to each local image and the 3D position error can be solved from multiple distance errors to different subimages.

If the subimages are small, we can assume that azimuth and elevation angle to all the targets in the subimage are similar and use the weighted target positions as the subimage center position. At this point we have a distance error from each radar position to each subimage. The number of subimages is large and we only have three unknowns (x, y, and z position errors), and we can set up an overdetermined system of equations to solve for the 3D position error from the distance errors and known subimage center positions.

Calculating the 3D position error from distance errors to each subimage would require solving a non-linear system of equations due to distance calculation not being linear, but assuming that 3D position error is small it can be linearized which makes solving it much easier and faster.

Knowing the subimage center azimuth and elevation angles, the distance error $\Delta r_{n,k}$ from $n$th radar position to $k$th subimage center can be written as a 3D Cartesian vector: $[\Delta r_{n,k} \cos \theta_{n,k} \cos \varphi_{n,k}, \Delta r_{n,k} \cos \theta_{n,k} \sin \varphi_{n,k}, \Delta r_{n,k} \sin \theta_{n,k}]^T$, where $\varphi_{n,k}$ is azimuth angle from $n$th radar position to $k$th subimage center ($0$ to $2\pi$) and $\theta_{n,k}$ is elevation angle ($-\pi/2$ to $+\pi/2$), note that this is different from the usual spherical coordinate definition that uses inclination. Assuming that $\Delta r_{n,k}$ is small then the target azimuth and elevation angles are almost the same before and after the shift and the linear system for solving the 3D position error at $n$th position can be written as:

$$\mathbf{R_n} = \mathbf{M_n} \Delta \mathbf{x_n}$$

$$\mathbf{M_n} = \begin{bmatrix}\cos \theta_{n,0} \cos \varphi_{n,0} & \cos \theta_{n,0} \sin \varphi_{n,0} & \sin \theta_{n,0} \\ \cos \theta_{n,1} \cos \varphi_{n,1} & \cos \theta_{n,1} \sin \varphi_{n,1} & \sin \theta_{n,1}\\ ... & ... & ...\\ \cos \theta_{n,k} \cos \varphi_{n,k} & \cos \theta_{n,k} \sin \varphi_{n,k} & \sin \theta_{n,k} \end{bmatrix}, \, \mathbf{R_n} = \begin{bmatrix}\Delta r_{n,0} & \Delta r_{n,1} & ... & \Delta r_{n,k}\end{bmatrix}^T, \, \Delta \mathbf{x_n} = \begin{bmatrix} \Delta x_n & \Delta y_n & \Delta z_n \end{bmatrix}^T$$

$\mathbf{M_n}$ is a Kx3 matrix of subimage center angles, $\mathbf{R_n}$ is Kx1 matrix of distance errors to each subimage, and $\Delta \mathbf{x_n}$ is 3x1 matrix of 3D position errors.

Solving the linear system for $\Delta \mathbf{x_n}$ at each radar position gives the desired 3D position error.

Weighted Least Squares

In a real SAR image signal-to-clutter ratio can vary a lot between different targets. To get the most accurate estimate measurements should be weighted by the signal-to-clutter ratio. The calculation for approximate of the signal-to-clutter ratio from the target demodulated phase is quite involved and the full details can be found in paper: "Weighted least-squares estimation of phase errors for SAR/ISAR autofocus" by Wei Ye, Tat Soon Yeo and Zheng Bao.

The final result is that weighting factor $w_p$ for each target in GPGA can be written as:

$$w_p = \frac{1}{\sigma_p^2} = \frac{d}{4 c^2 - 2d - 2 c \sqrt{4 c^2 - 3 d}}$$

$$d = E(|g_{n,p}|^2),\, c = E(|g_{n,p}|)$$

Weighting factor equals $1/\sigma_p^2$ which is the inverse of variance of the phase error in the measurement from target $p$. This weight should be used to weight each target in GPGA phase gradient estimation.

In 3D trajectory estimation the weighting factor is the combined weight of all targets in the subimage. It can be calculated as:

$$w_k = 1 / \sum_{p} 1 / w_p$$

GPGA 3D trajectory deviation estimation

GPGA algorithm with 3D trajectory deviation estimation.

Putting it all together the algorithm is quite computationally demanding due to multiple image formations required. They could be skipped in some cases, but the best performance is obtained when a new image is formed after every iteration to get a better estimate of true target locations. However, when using fast factorized backprojection it's quite fast when implemented on GPU even with a large amount of data.

Compared to other autofocus algorithms I believe this is one of the most general ones. It computes the 3D position error, it doesn't assume linear track and can work with any shaped flight track, it can correct for position error that exceeds range resolution, it works with digital elevation model, and it can be extended to work with 3D imaging SAR or bistatic SAR systems.

I implemented the algorithm on GPU using custom CUDA kernels and despite it's heavy computation requirement it runs very quickly. In practice even just few iterations result in a large improvement in image quality and it's much more efficient than the Minimum entropy autofocus that I previously used.

The code is open source and available as "gpga_bp_polar_tde" function in torchbp package.

Synthetic example

Ideal SAR image of the point targets without any position error (left). Position error added to the image (right), Y-axis linear trend is removed.

I made a small synthetic example with nine point targets in a grid. The height of the radar was set to 20 m and it moves linearly along Y-axis sampling every quarter wave length (12.5 mm / 0.5 inch). I added random low frequency 3D position error to the radar position and used the corrupted position to form the initial SAR image.

Image with position error (left) and the same image after applying the autofocus algorithm (right).

The maximum position error is 0.1 meters and it causes the image to be extremely defocused. Position error causes sidelobes to appear around each target.

The image was divided into nine subimages for autofocus so that each point target is in its own image. After applying six iterations of the autofocus algorithm the solved image looks almost exactly like the error-free ideal image.

Solved 3D position error (left) and error in solved position in wavelengths (right).

The solved 3D position error matches well to the error that was added. The maximum error is 0.1 wavelengths in Z-direction and RMS error is 0.0007 wavelengths. The image quality is the most sensitive to X-direction error that changes the measured distance the most, Z-axis error causes the smallest error in this case with low look angle as Z-axis is mostly perpendicular to the distance to the target.

Real data example

Camera image of the scene. This is from a different day and little farther away to capture more of the scene in the same image.

For a real data example I flew the radar drone in a straight line at 5 m/s velocity at 110 m altitude. The radar recorded full quad (HH, HV, VH, VV) polarizations with all four polarizations sampled at 1.8 ms repetition interval. The total number of samples is 20,000 for a total track length of 180 meters and 36 seconds of data capture time.

SAR image without autofocus using only the IMU and GPS for the radar position.

Without any autofocus algorithm and just relying on the GPS and IMU data fusion results in very poor quality image. The reported GPS position horizontal dilution of precision (HDOP) is on average 0.5 which is very good, but it's still not good enough for SAR accuracy requirement. RTK GPS would be much more accurate, but it requires a ground station and there isn't a small enough RTK GPS module that would fit well on the small FPV drone I'm using.

The same image after autofocus with GPGA 3D trajectory estimation.

After GPGA 3D trajectory deviation autofocus algorithm the image quality is much better. The image isn't still perfectly focused and it shouldn't be expected to, because no digital elevation model (DEM) is used. Instead every target is assumed to be on a flat plane at zero height. This assumption does not hold for a real scene as buildings and trees are at higher elevation than the ground and there is some elevation difference of the ground at different locations in the image.

Solved position error.

The Z-axis solved position error is very large and it's unlikely that the real Z-axis error in the drone's flight elevation is this big and the error is likely due to the flat-plane assumption. If I disable Z-axis error estimation and force it to be zero the image quality is worse. For a better comparison here's a link to image with Z-axis correction for reference and also the image without autofocus.

The raw image dimensions are 6663 range samples by 13935 azimuth samples, requiring a total of $6663\times13935\times20000 = 1.9\times10^{12}$ backprojections to form the image when using ordinary backprojection. Using fast factorized backprojection image formation takes just 1.3 seconds on RTX 3090 Ti GPU, which is about 10 times faster than non-factorized backprojection. The final fully polarized image takes four times longer as it requires generating image for each of the four polarizations.

Autofocus uses a smaller image size of 2333 x 12541 pixels and divides it into 10x10 grid for a total of 100 subimages. Autofocus is only calculated for one polarization and the same solved position is used also for the other polarizations. The starting lowpass window size is 2000 samples and it's reduced by a factor of 0.7 every iteration until it's below 10 samples. The total number of iterations is 15 and the calculation takes a total of 17.5 seconds. It's a significant increase compared to the time it takes to form a single image due to requiring multiple image formations, but since the image formation is so fast when implemented on GPU it doesn't matter that much. Less iterations could work in this case, but in general these settings work well.

Antenna pattern normalization

Patch of ground illuminated by the radar. Three different areas for normalizing the reflectivity are colored.

The received power from a target depends on the target's distance to the radar, location in the antenna beam, and the radar reflectivity of the target. Radar reflectivity is what we want to determine and amplitude variations caused by the distance and antenna pattern is something that should be removed from the radar image.

Received power of a single radar pulse from a target can be written as:

$$P_r = C \frac{\sigma G_{rx}(\theta, \phi) G_{tx}(\theta, \phi)}{r^4}$$

$C$ is a constant that includes transmit power, receiver gain and other radar constant factors affecting the received power, $G_{rx}$ is the receiver antenna gain, $G_{tx}$ is the transmitting antenna gain, $r$ is the distance from radar to the target, and $\sigma$ is the radar reflectivity of the target.

Amplitude of the received signal is proportional to square root of $P_r$. It would be possible to add normalization in the backprojection calculation, but it's more efficient to calculate backprojection of the power received from a reference reflectivity separately:

$$P_{ref} = C \sum_{p \in \mathcal{P}} \sum_{n=1}^N \frac{\sigma_{ref} G_{rx}(\theta_n, \phi_n) G_{tx}(\theta_n, \phi_n)}{r^4}$$

$\mathcal{P}$ is the set of pixels in the image, $N$ is the number of radar measurements, $\theta_n$ and $\phi_n$ are elevation and azimuth angles to the pixel at $n$th position, and $\sigma_{ref}$ is the reference reflectivity where we want to normalize.

Removing the antenna pattern and distance variation from SAR image $I$ using $P_{ref}$ can be done by simply dividing the squared image by the reference power:

$$\sigma_0 = \frac{|I|^2}{P_{ref}}$$

$P_{ref}$ can be calculated on a coarser grid and number of sweeps can be decimated since antenna pattern doesn't change very fast making it faster to calculate than image backprojection.

We could simply set $\sigma_{ref} = 1$ and this is valid option if we want to normalize to point targets, but depending on how exactly the ground reflectivity is defined some other options are also available. Reflectivity of the ground can be defined in multiple ways. The most common one is to define $\sigma = \sigma_0 A_{\sigma}$, where $\sigma_0$ is the radar reflectivity of ground per unit area and $A_{\sigma} = \delta x \delta y$ is the area of the patch on the ground.

The size of the patch that needs to be considered is the pixel resolution in the SAR image. Radar measures radials distance, which means that $\delta_r$ is a constant that depends on the radar parameters. The angular resolution of the radar $\delta_\varphi$ is constant, so $\delta y = 2r\sin(\delta_\varphi/2)$. For SAR image with non-isotropic antenna the resolution isn't as good, but antenna weighting is already included in the calculation and we can use the resolution with isotropic antenna.

This means that to normalize to ground reflectivity $\sigma_0$ we should set:

$$\sigma_{ref} = A_{\sigma} = \delta_x \delta_y = \frac{\delta_r 2 r \sin(\delta_\varphi/2)}{\sin(\theta)} = C \frac{r}{\sin(\theta)}$$

Constant factor $C$ can be merged with the constant factor in the $P_{ref}$ calculation. To avoid dividing by zero at zero ground range we can limit the $\theta$ used in calculation to angular size of the first resolution cell: $\theta_{\text{max}} \approx \arcsin(z/(z+\delta r)) \approx \pi/2 - \sqrt{2\delta_r/z}$.

$\beta_0$ or $\gamma_0$ can be calculated the same way by changing the $\sigma_{ref}$ definition. $\beta_0$ doesn't include any correction for the grazing angle and $\sigma_0 = \beta_0 \sin\theta$. The third definition is to calculate $\gamma_0 = \sigma/A_\gamma = \beta_0 \tan \theta$. This normalizes for the area of the patch that the radar sees. If the ground reflectivity would be completely diffuse so that it reflects equally well in all directions, then the reflected power only depends on the area of the target that the radar sees and only this definition would result in no incidence angle variation in the image.

The previous measurement after removal of range and antenna pattern caused amplitude variation. The reflectivity is normalized to sigma zero.

After normalization the resulting image is much flatter in amplitude and at the edges where the signal-to-noise ratio is lower the noise floor is raised to visible level. Absolute radiometric calibration is not done since the constant $C$ has not been determined. It would require measuring a known reflectivity target and based on that measurement the $C$ constant can be determined. Incidence angle was calculates assuming a flat ground.

For comparison the same image with gamma zero is slightly brighter at farther distances where the grazing angle is low. Beta0 image looks very similar to the sigma0 image, there's only difference at extremely close ranges. Here's also a clickable link to sigma0 image. I recommend opening them in separate tabs for easier comparison.

The first option of just setting $\sigma_{ref}=1$ results in very similar image to gamma zero normalization, only differing at very close distances. It turns out that at low grazing angle they are the same up to a constant.

Visualized $P_{ref}$ for the previous image for VV polarization.

Plotting the image of $P_{ref}$ shows how the antenna illuminates the ground. The flight height was 110 m and the antenna was angled at 10 degrees below the horizon and the antenna boresight should hit the ground at 600 m distance. However, the best signal to noise ratio is obtained at 100 m since it's closer to the radar and antenna gain is still quite good at that angle.

Simulated antenna pattern was used in normalization and especially at far away angles from the boresight the actual radiation pattern can differ significantly. The uncertainty in antenna pattern causes amplitude difference at different angles, and in the polarimetric case the antenna pattern for H and V polarizations is slightly different which can cause errors in the relative channel amplitudes.

Polarimetric calibration

Block diagram of the radar with error sources affecting the measured polarization labeled.

A fully polarized radar measures four polarizations: HH, HV, VH, and VV. The first letter is the polarization of the transmitter, the second one is the polarization of the receiver, and V and H stand for vertical and horizontal. This is enough information to fully characterize the polarization response of a target and allows calculating received power for an arbitrarily polarized receiver antenna when the target is illuminated with an arbitrary polarization.

The transmission and reception of the different polarizations are implemented by a switch that selects which polarization is transmitted or received. The same electronics are used for all polarizations which results in good amplitude and phase match across all frequencies. However, due to polarization switches, slightly different lengths of SMA cables between switches and antennas, and small differences between the antennas, there are amplitude and phase differences between the polarizations. Additionally, the limited isolation of the switches and antennas causes some crosstalk between different polarizations.

To make accurate polarimetric measurements, channel amplitude and phase differences as well as crosstalk need to be measured and calibrated out. The effect of receiver and transmitter errors can be modeled as (Ainsworth, et. al):

$$\begin{bmatrix} O_{HH} & O_{HV}\\ O_{VH} & O_{VV}\end{bmatrix} = \begin{bmatrix} r_{HH} & r_{HV}\\ r_{VH} & r_{VV}\end{bmatrix} \begin{bmatrix} S_{HH} & S_{HV}\\ S_{VH} & S_{VV}\end{bmatrix} \begin{bmatrix} t_{HH} & t_{HV}\\ t_{VH} & t_{VV}\end{bmatrix}$$

$[O]$ is the observed polarization, $[S]$ is the true target scattering matrix, and $[t]$ and $[r]$ are matrices that model how the scattering matrix is transformed during the measurement by transmitter and receiver.

The previous equation can be written also in form:

$$ \begin{bmatrix}O_{HH}\\O_{HV}\\O_{VH}\\O_{VV}\end{bmatrix} = \mathbf{M} \begin{bmatrix}S_{HH}\\S_{HV}\\S_{VH}\\S_{VV}\end{bmatrix} $$

$\mathbf{M}$ is a 4x4 complex valued matrix that contains all the error terms that affect the target measurement.

A simple error correction method is to assume that there is no crosstalk and that absolute radiometric correction is already done. In which case $\mathbf{M}$ can be written as:

$$\mathbf{M} = \begin{bmatrix}k\alpha&0&0&0\\0&1/\alpha&0&0\\0&0&\alpha&0\\0&0&0&k^{-1}\alpha^{-1}\end{bmatrix}$$

$\alpha$ corrects for the imbalance of $HV$ and $VH$ measurements and $k\alpha$ corrects for $HH$ and $VV$ imbalance. Due to reciprocity, we should have $HV = VH$ and we can solve for $\alpha$ from the measured data by calculating the amplitude and phase difference between the measured $HV$ and $VH$ polarizations. Calculating the correlation matrix $C = E(O O^\dagger)$, where $E(\cdot)$ calculates the mean over all pixels in the SAR image and $\dagger$ is conjugate transpose, we can solve for $\alpha$:

$$\alpha = \left|\frac{C_{VHVH}}{C_{HVHV}}\right|^{1/4} \exp(j\text{Arg}(C_{VHHV})/2)$$

For example: $C_{VHHV} = E(O_{VH} O_{HV}^*)$. This calibration was already performed in the previous images so that the HV and VH channels could be summed for visualization (with $k=1$). Determining the $k$ factor is harder and requires measuring a target with a known scattering matrix, usually a corner reflector.

Scattering matrices of trihedral and dihedral corner reflectors at various angles. By measuring a known target, the polarimetric calibration matrix can be solved.

This simple measurement is enough to calibrate the biggest error sources, but for more accurate result the crosstalk terms should also be solved. There are several different polarimetric calibration methods and the one I decided to implement is "Orientation angle preserving a posteriori polarimetric SAR calibration" by T. L. Ainsworth, L. Ferro-Famil and Jong-Sen Lee. This method works by calculating correlation matrix from a SAR image of a scene, and only assuming scattering reciprocity (HV=VH) calculates most of the error terms based on the expected form of the correlation matrix. However, even with this method, at least one measurement of a known target is required to determine the $k$ calibration factor.

The previous image with polarimetric calibration.

After the polarimetric calibration, the largest difference is that the HH and VV channel amplitude balance was corrected increasing the VV channel power making the image redder compared to the uncorrected image.

Pauli decomposition of the calibrated image.

After calibration, polarimetric decompositions, such as Pauli decomposition, can be applied. This is often used presentation for SAR data since it can be interpreted physically. The three channels are: HH+VV, which corresponds to targets where H and V polarization return at the same phase, for example a sphere or trihedral corner reflector. HH-VV corresponds to a dihedral reflector at 0 degrees, where one of the polarizations is flipped in phase. The last channel VH+HV corresponds to targets that return orthogonal polarization, such as 45 degree oriented dihedral reflector.

For surface targets, HH+VV corresponds to single or odd number of bounces, and HH-VV double or even number of bounces. Targets that depolarize the reflection, such as tree canopy are visible on the HV+VH channel.

Full SAR image with Pauli decomposition and without antenna pattern normalization.

In the fully zoomed-out image, quite lot of details can be seen even at long distance, but the grazing angle at far away is very low, so only tree tops and buildings are visible and shadowing is severe. This is without antenna pattern normalization, since it doesn't make sense to normalize to flat ground that isn't visible at long range, but the polarimetric calibration is still applied.

Buildings at (+250 X, -1000 Y) with lot of sharp corners look very different from the surrounding trees and grass, which reflect a lot of cross-polarization. Using polarimetric image, it's possible to classify the target response, such as vegetation or artificial targets, which is one of the main uses of polarimetric SAR imaging.

VideoSAR

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When a long radar measurement is divided into multiple short images, the result can be turned into a video. The drone flew autonomously a circular pattern over a field while the radar recorded continuously. Afterwards I autofocused and generated SAR images of short sections of the data, then synced them with the GoPro recording. The video is played back at 2x speed.

Each image has 2048 radar measurements, with 75% overlap between consecutive images. Having more data in each frame improves the image resolution and decrease the amount of noise, but lowers the frame rate in the video. The high overlap increases the frame rate as a new frame can be created when there is 25% of new data instead of waiting for a full window size and allows for good quality image with reasonable frame rate.

Each frame is autofocused individually and the solved position is used for the future frames. Apart from this, no inter-frame stabilization is performed. There are some small geometric errors, but overall the stability between frames is quite good. Antenna pattern is normalized to gamma0 and image edges with low SNR are cut out. Radial lines appear on some frames caused by RF interference.

Urban scene

I captured another scene with more buildings. The drone flew in a straight line at height of 110 m and a speed of 5 m/s for 72 seconds, covering a total track length of 360 m. During this time the radar captured 40,000 sweeps.

Camera image of the scene.

Image of urban scene after autofocus, antenna pattern normalization, polarimetric calibration, gamma zero normalization, and Pauli decomposition visualization. The camera image is taken from approximately X=100 m.

Autofocus required 41 seconds for this scene, and image formation took 2.3 seconds per polarization. The resulting image is 6663 by 27863 pixels. Autofocus improves the image quality significantly. Without autofocus the image is badly unfocused.

Conclusion

A complete software pipeline for autofocusing and calibrating polarimetric SAR image was presented. Autofocus algorithm that uses generalized phase gradient autofocus (GPGA) and 3D trajectory deviation estimation to solve for the 3D position error was introduced. Using GPU accelerated fast factorized backprojection even very large SAR images can be focused very quickly.

The resulting image quality is very good especially considering that this might be one of the cheapest drone mounted SAR systems.

The software is open sourced and available at: https://github.com/Ttl/torchbp.

Designing a low-cost high-performance 10 MHz - 15 GHz vector network analyzer

2025-04-15T00:00:00+03:00

Introduction

VNA PCB.

Vector network analyzer is a device used to measure scattering parameters of electrical circuits operating at high frequencies. S-parameters tell how much a circuit reflects power back to the source and how much it attenuates or amplifies it to the other ports. Working with S-parameters is an essential part of designing any electronics operating at GHz frequencies.

These devices aren't cheap, especially as the operating frequency increases. High end VNAs that operate at millimeter-wave frequencies can cost several hundred thousand dollars, and even affordable lower-frequency devices are expensive.

My two previous homemade VNAs.

In 2016, I made my first cheap 10 MHz to 6 GHz two-port vector network analyzer. At the time, there were no cheap VNAs available, and I had to design one myself. It was functional but had high leakage between the two ports, causing big measurement inaccuracies, which resulted in unusable accuracy for many measurements. The next year, I designed improved version that had better performance and was actually useful. I have used it since for my own projects, but lately, it has started to feel limiting, and I wanted to either buy or make a better VNA. I would want to have higher maximum frequency, hopefully >10 GHz, better measurement accuracy, and good port-to-port isolation.

nanoVNA (left) and LibreVNA (right).

Nowadays, there are many cheap commercial VNAs. The most popular is probably nanoVNA. There are several different versions of it, but they are mostly limited to around 1 - 4 GHz, which is not enough for me. It's also a so-called 1.5-receiver design that can only measure S11 and S21, requiring manually flipping the device being measured to fully measure the two-port S-parameters. It isn't any better than what I already have. There are also several other 1.5-receiver VNAs, some better and some worse, but the 1.5-receiver architecture is too limiting and results in inaccurate measurements to be worth considering.

A step up on that is LibreVNA. It's a 100 kHz to 6 GHz two-port VNA that was partly based on my previous VNA design. It has better performance than my previous 6 GHz VNA, but the performance isn't as good as I would want. There is quite high leakage above 3 GHz that limits the measurement accuracy. Unlike the nanoVNA, it's a proper two-port VNA that can measure two-port S-parameters without manually requiring flipping of the device. However, it's a three-receiver design instead of a better-performing four-receiver design. There is a shared reference receiver before the port switch that is used for measuring the output signal instead of two separate reference receivers for each port. Using advanced calibrations such as TRL, and unknown thru requires a two-port VNA with four receivers. These are very useful as they relax the requirements on how well the calibration kit needs to be known, increasing the measurement accuracy, especially when using a low-cost, inaccurate calibration kit.

Keysight E5603 VNA. 100 kHz to 18 GHz option has a list price of 53,000 € and this isn't even a high-end model.

There are better performing VNAs that would be perfect for my requirements, such as those from Copper Mountain or Keysight, but even the cheapest >10 GHz VNAs are over ten thousand dollars.

I was unable to find a cheap two-port VNA that would meet my requirements, but after thinking it a bit, I was quite sure that I could make my own VNA that would have better performance than any other cheap VNA currently available, even when factoring in the higher prices at small prototype quantities.

VNA architecture

Generic block diagram of a four receiver VNA.

A typical VNA consists of excitation and local oscillator signal sources. The source is routed through a port switch to one port, with the other port being terminated to 50 ohms. The signal then passes through directional couplers, which sample the incident and reflected waves. These waves are mixed with the local oscillator to convert them to low frequencies that can be sampled with an ADC. These measurements can be used to calculate both the amplitude and phase of the reflected and transmitted waves.

A major issue with this architecture is the port switch. It requires >100 dB isolation over the whole operational bandwidth of the VNA, which is very hard to achieve, requiring that several RF switches in their separate shielded enclosures are put in series. Especially at >10 GHz RF switches, shielded enclosures, and amplifiers can get quite expensive.

Traditionally, designing a wideband RF signal source has also been a challenge. Often requiring multiple mixers, oscillators, filters, and frequency multipliers to achieve high-quality signal over the entire VNA frequency range. However, nowadays there are cheap PLL chips with integrated bank of VCOs that can generate signals over very wide frequency range. For example, LMX2594 is a 10 MHz to 15 GHz RF signal source in a single package that costs $38 at large quantities.

Block diagram of dual-source VNA.

Using integrated phase-locked loop (PLL) ICs for the source signal generation makes it possible to remove the port switch and instead have separate signal sources for each port. This is both cost-effective and simplifies achieving the isolation requirement.

The drawback is that variable attenuator for source power level control and filter bank for filtering the harmonics needs to be duplicated for each port. However, if low adjustable source power range is acceptable, the external variable attenuator can be removed, and the internal power adjustment of the PLL chip can be used instead. The LMX2594 output power can be adjusted by about 10 dB.

Filter bank can also be removed if harmonics are acceptable. Ideally, harmonics shouldn't affect the S-parameter measurements when measuring linear devices. However, in practice there can be some non-linearity in the receiver that causes harmonics to mix to the fundamental frequency. Including the filters would slightly improve the measurement quality.

After looking at the prices of variable attenuators and RF switches at 15 GHz, I decided that I'm fine with the harmonics and low output power adjustment range.

Directional couplers

Directional coupler schematic.

VNA needs directional couplers to sample the incident and reflected waves at both ports. These couplers should also operate from 10 MHz to 15 GHz with good directivity and low loss. The standard directional coupler used in many commercial VNAs is a resistive directional bridge. It requires a balun, which in this case is implemented with a coaxial cable surrounded by ferrite beads to extend its operation to low frequencies.

In my previous VNA, I used a similar directional coupler but it only had one coupled port. I realized that in this application, when two couplers are needed that sample reverse and forward waves, two couplers can be put back-to-back sharing the same coaxial cable balun, which makes it smaller.

Directional coupler breakout PCB.

I made a breakout PCB of the coupler so I could measure it as its performance is very important for the VNA. PCB material is FR4, which is quite lossy at high frequencies, but proper RF material would be too costly.

Measured S-parameters of the coupler. Ports 1 and 2 is the thru path, and ports 3 and 4 are coupled ports.

I measured the coupler with my previous 6 GHz VNA, and the performance looks good. It's a four port, but this is not a problem and only requires making multiple measurements. Loss is 3 dB at low frequencies and 5 dB at 6 GHz. Directivity is about 20 dB, which is fine but could probably be improved with slightly tuning the resistor values. Isolation between the coupled ports is acceptable, and there doesn't seem to be issues with sharing the balun.

Receiver

ADL5961 block diagram. This would be an ideal receiver for the VNA if it wasn't for the price. It has integrated directional coupler and even LO frequency dividers and multipliers.

The receiver needs to first down-convert the RF signals from the directional coupler and then sample it with an ADC. Finding a wideband mixer turned out to be problematic. ADL5961 would be an ideal choice as it's rated from 10 MHz to 20 GHz, it's designed for VNA applications, and even includes a directional coupler on the chip. The drawback is that it costs $200 for a single chip, and two of them (one for each port) would cost more than all the other components combined.

The other options are very limited. Many mixers function at high enough frequencies, but almost all of them also have high minimum frequency. I could have two mixers for low and high frequencies that are switched, but it would cost too much. Some mixers could have enough conversion gain at low frequencies even if operated out of spec, but I don't want to test them individually. Another option would have been to make my own mixer with diodes, but this would require a large amount of testing and the resulting circuit would likely be much larger than the small commercial integrated circuits.

ADL5802 dual channel mixer block diagram.

In the end, I chose to use ADL5802, which is only rated from 100 MHz to 6 GHz. Unfortunately, this limits the performance at high frequencies when everything else would work fine. However, I don't see other cheap options. They main benefit of it is that it's cheap ($12 / piece at high quantities) and it has two mixers in one package, further driving down the cost. The reason I chose to use it is that it does have some performance figures listed at 8 GHz that suggests that it has 5 dB lower conversion gain than at 6 GHz. Even if it doesn't function well above 8 GHz, this should be good enough as I mostly currently work at frequencies under 7 GHz.

ADC

Receiver dynamic range plot (not to-scale).

The dynamic range of the analog-to-digital converter (ADC) is critical because it often limits the receiver's dynamic range. The mixer output can vary from the noise floor (approximately -160 dBm/Hz) to about +10 dBm at maximum input power at the 1 dB compression point. This wide dynamic range exceeds what most ordinary ADCs can handle. The ADC's dynamic range depends on the noise in a single sample and the number of samples averaged. Faster low-bit ADC can be more accurate than slow many-bit ADC when many samples are averaged.

The mixer output frequency should be at least a few hundred kHz to minimize the effects of phase noise and 1/f noise. A higher intermediate frequency (IF) allows for shorter measurement times, as at least few cycles of the IF must be sampled. Some margin should be also left for the ADC's anti-alias filter roll-off. A higher sampling rate also improves spectrum analyzer performance but increases the ADC cost.

The key performance metric for the ADC's dynamic range is noise spectral density (NSD). Many ADCs instead report signal-to-noise ratio (SNR) of a single sample instead. Using the sampling rate, NSD can be calculated as:

$\text{NSD} = -\text{SNR} - 10\log_{10}(f_s/2)$

where $f_s$ is the sample rate. Typically its around -140 to -160 dBFS/Hz (noise floor decibels relative to the ADC full-scale input at 1 Hz bandwidth). In practice this figure tells the FFT noise floor of the ADC output as function of measurement length. For example, with a 0.1-second measurement time and an NSD of -140 dBFs/Hz, the FFT noise floor is -130 dB below the full-scale non-clipping input.

The ADC I chose to use is AD9238 which has 40 MHz maximum sampling frequency and an NSD of -143 dBFs/Hz. Since the ADC's dynamic range is less than dynamic range of the mixer's output dynamic range, either high input causes ADC saturation or the ADC's noise floor is above the mixer's noise floor. In this case it's a bit of both.

With an NSD of -143 dBFs/Hz, if the incident wave power is at -10 dBFs level at the ADC input, the dynamic range for S21 measurement is at most 133 dBFs/Hz since it's calculated as the ratio of port 2 received power divided to port 1 incident power. With a 10 Hz IF bandwidth, the S21 measurement will have a noise floor of -123 dB. If the source power is lower, the incident power decreases, and the S21 noise floor increases.

If the cost is not an issue, better choices are available. For example, the AD9650 (105 MHz version) has an NSD of -160 dBFs/Hz. It would increase the dynamic range by about 17 dB. It's also about ten times more expensive, so the performance doesn't come cheap.

FPGA

FPGA digital signal processing block diagram.

Fast sample rate ADCs need an FPGA to handle the high amount of data they produce. The same FPGA can also handle all the DSP and I/O control functions, avoiding the need for adding a separate microcontroller.

The digital signal processing needed inside the FPGA is deceptively simple. The input signal from each of the four receivers is a signal at a few MHz frequency. It's multiplied with a sin and a cos of the same frequency signal to get a zero frequency I and Q output signals that are summed. At the end of the sampling period, these I and Q accumulated sums are divided by the number of samples summed to get the average value. This is equal to calculating just a single bin of Fourier transform and is the optimal way of calculating magnitude and phase of a signal at a known frequency.

The rest of the logic on the FPGA is timing, switching I/O signals, and communicating with the PC. All of the logic and calibration is implemented on PC as it's much easier to do there.

PCB

Partially assembled VNA PCB.

PCB has 6-layers and is made from FR4 material. FR4 is fine in this application since distance from signal source to output port is quite short and there aren't any sensitive circuits such as distributed filters that are sensitive substrate material variations.

For good isolation RF enclosure is necessary and it requires mounting holes and contact surfaces on the PCB. Isolation was the biggest issue with my previous VNA and I did everything to make sure that this time the leakage signal will be below the noise floor. Due to the high frequency all the RF signals are routed at the top layer, requiring routed channels in the shield to pass the signal via the different enclosures.

Assembled VNA.

I ordered the PCB assembled but I had to assemble some components such as mixers, SMA connectors, and couplers myself. When considering a large scale production the couplers are especially tricky as they require manually cutting a coaxial cable, inserting ferrite beads into it, and the soldering it to the PCB. In this case it isn't an issue when I just make one PCB for myself, but this would be difficult for mass manufacturing.

CNC machined case

CNC machined case, upper half.

I first made a 3D printed case lined with aluminium foil for testing the electronics and making sure the mechanical design fit the PCB. It had quite good isolation after I figured how to get the aluminium foil lining to be tear free. Stability and thermal properties of the CNC machined case should be much better, so I ordered the same design machined from aluminium.

VNA with the aluminium case.

The case consists of upper and lower pieces with the PCB being sandwiched between them. I designed it to be simple so that it can be manufactured on a 3-axis CNC machine in a single pass and without any threads. The cost was $75 for the case, $37 for shipping, and $29 for taxes. Not bad for a fairly large piece of aluminium.

Uncorrected S-parameters with short on port 1 and load on port 2. 200 Hz IF bandwidth.

The leakage with the CNC machined case was surprisingly high when I first assembled it. Uncorrected S21 was higher than -70 dB at 6 GHz. The culprit turned out to be a gap between the edge launch SMA connectors and the aluminum case. The gap between the connector and the case is very small, less than 1 mm, but it works as an antenna just well enough that the coupling to the other port was about -70 dB.

Solder wick and aluminium foil used to seal the gap between the SMA connector and the aluminium case.

I used aluminium foil to plug the gap between the bottom case half and the connector. A small folded up piece of foil placed under the PCB compresses nicely and provides good RF seal. The upper half can't use the same method since it would short the signal conductor. I used instead a small piece of solder wick to seal the upper half gap.

I knew that this connector gap could be an issue when I first designed the VNA, but I decided to go with it because the alternative of using a bulkhead SMA connector (the whole connector goes through the case) was just too much trouble. Bulkhead connectors would need a hole and threads in the case in 90-degree angle from the current machining direction. Bulkhead connectors would also need to be soldered to the PCB when it's mounted in the case, making it inconvenient for prototyping.

Uncorrected S-parameters with short on port 1 and load on port 2 with EM gasket. 10 Hz IF bandwidth.

After plugging the gap, the isolation is much better and leakage is below the noise floor at all frequencies even with very low 10 Hz IF bandwidth (0.1 s measurement time per frequency point).

The noise floor increases as the source frequency rises. This is because the mixer's conversion gain decreases beyond 6 GHz. The dynamic range is still quite good up to about 10 GHz, but starts to quickly decrease after that. While the dynamic range was 120 dB at low frequencies, it's less than 70 dB at 15 GHz.

Calibrated S-parameters with short circuits on both port 1 and port 2. 10 Hz IF bandwidth.

After the calibration, the dynamic range is slightly lower at high frequencies due to the losses that need to be calibrated out, but the difference isn't large due to directional couplers still working with acceptable performance. While the lower dynamic range at high frequencies might not be good enough for precision measurements, it's still useful for many basic measurements.

Harmonic mixing

Reference receiver measurement at different LO harmonics (arbitrary scale).

Mixer is rated only up to 6 GHz operation and it has an integrated LO amplifier. At high enough frequencies the LO amplifier's output power isn't high enough to drive the mixer core. If the LO is driven at for example 1/3 of the desired frequency, the fundamental frequency should be high enough to still pass through the integrated LO amplifier and there should also be some harmonic mixing products at the output caused by the third harmonic of the LO.

I swept the source from 0.1 GHz to 15 GHz with LO set to different harmonics. The results of the reference receiver power (arbitrary scale) are shown in the image above. The result is magnitude of the mixer's output, which is proportional to source power coupled into reference receiver and the conversion gain of the mixer, so this measurement doesn't just measure the mixer. As expected, the fundamental frequency results in the highest conversion gain at the mixer's operational range. The IF signal is about 15 dB lower at 10 GHz, which is still acceptable, but above that it starts to drop quickly. The output also becomes very noisy, likely due to LO drive power being too weak. At around 12 GHz, using the LO at 1/3 frequency for 3rd harmonic mixing results in higher output power. Other LO harmonics than 1st or 3rd results in lower conversion gain.

The LMX2594 chip seems to have a 2 dB dip in output power from 1.25 GHz to 1.875 GHz when the output frequency divider value is set to 6. This dip is visible in all traces at that frequency range due to source power being lower. The same effect due to LO source power can also be seen at higher frequencies at different LO harmonics.

Some VNAs use a similar trick with source harmonics to extend the maximum frequency range. For example, to measure S-parameters at 20 GHz, set the source to 10 GHz and use the 2nd harmonic of the signal as the test signal. The LO would be set to (20 GHz + IF frequency)/3 = 6.67 GHz for the LO 3rd harmonic. However, this method can't be used to measure any even slightly non-linear devices, as the non-linearity of the device would cause the harmonics to change due to the strong fundamental signal that is still present. Similarly, the receiver's non-linearity can cause issues. Driving mixer LO with harmonics doesn't suffer from the same issues.

Stability

Temperature of the FPGA.

The board does get quite hot, I estimated that it dissipates about 10 W of power. The FPGA's internal temperature sensor indicates a die temperature of 64 C (147 F). The case also gets uncomfortably warm to touch. It takes about 1 hour to reach the equilibrium temperature.

Uncorrected S11 of short at 6 GHz as the VNA warms up.

Temperature has an effect on the measured S-parameters. With a short circuit at port 1, uncorrected S-parameters measured at 6 GHz changed from -4.43 dB at room temperature to -4.58 dB when warm (this includes VNA internal losses and external 0.5 m long SMA cable loss). Source power should drop at high temperatures, but since S11 is a ratio, it should cancel out. Incident and reflected wave mixers are in the same package, well-matched to each other, and at the same temperature, so their conversion gain change should also cancel out. This just leaves the coupler as the likely cause the drift.

One possible reason for thermal drift is that FR4 PCB dielectric constant and loss tangent can have large temperature variation. Copper resistance also increases with the temperature. The loss of coaxial cable is about 7% larger at 60 C than at room temperature, and microstrip lines on the PCB likely have even greater loss increase. Difference between incident and reflected waves is that the incident does not go through the coupler but reflected wave does, so it should be expected that the uncorrected S11 decreases slightly as temperature increases due to increased loss of the coupler. Resistors in the coupler also change slightly with the temperature.

I tried measuring the change in coupler's loss at different temperatures using the coupler breakout board and heating it up with a hot air tool. I don't have a thermal chamber at home, so the measurement accuracy is low but I did observe about 0.1 dB change in S21 when heating it to hot-to-touch temperature.

Another temperature effect is thermal expansion in coaxial cable and PCB, that mainly affects the phase. Even if only the amplitude of the result is important, phase accuracy is important since phase is used in calibration.

Uncorrected S11 of short at 6 GHz after the VNA temperature has stabilized.

After the temperature has stabilized, the measurements are quite stable. Keeping everything absolutely still, drift in uncorrected short S11 measurements is 0.0001 dB RMS in 10-minute measurement with 100 Hz IF bandwidth. Noise in a single measurement is 0.00006 dB RMS, limited only by the signal-to-noise ratio.

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In practice, achieving this accuracy is challenging. Moving the SMA cable changes uncorrected S11 by around 0.03 dB and it doesn't return to the original level when the cable is returned to the original position. Bending the cable can cause even larger changes. Connector repeatability, especially with low-quality SMA connectors, also has an effect on the measurement accuracy. Professional labs use expensive phase-stable cables and precision connectors for this reason.

Measurements

Self-made VNA calibration kit. Thru, short, open, and 50-ohm load.

For calibration kit, I'm using the same self-made short, open, and load that I made for my previous VNA. The calibration standards are measured with a commercial VNA that was calibrated with highly accurate calibration kit, and as a result they should be fairly accurate. Thru is an ordinary SMA through adapter, I don't have any measurement data of it, but that's not an issue since I'm using unknown thru calibration algorithm, which, as the name suggests, does not require a known thru standard.

Bandpass filter

6 GHz bandpass filter.

To test the accuracy of the VNA, I measured a 6 GHz bandpass filter with my VNA that was calibrated with the self-made calibration kit. The results were compared to measurements taken with a commercial VNA, calibrated with a proper calibration kit.

The bandpass filter has DEA165550BT-2230C2-H ceramic 6 GHz bandpass filter mounted on an FR4 PCB. Copper sheet was soldered over it to create an enclosure.

Bandpass filter S-parameters compared.

The S-parameters measured with my VNA closely match with those from the commercial VNA. I only plotted S21 and S11 to make the plot clearer, but S12 and S22 also agree well.

Bandpass filter S-parameters compared, passband detail.

Zooming into the passband, my VNA has less trace noise in the S21 than the commercial VNA. The commercial VNA should be more accurate and I suspect that this is caused by inaccurate thru standard definition in the SOLT calibration. It's old enough that it doesn't have unknown thru algorithm built-in. Ignoring the trace noise measured S-parameters agree with excellent accuracy.

Solved S-parameters of the thru calibration standard.

Unknown thru calibration solves for the thru S-parameters during the calibration. Plotting the solved thru S-parameters, the measurement looks high quality, but the performance of the thru doesn't look very good and it definitely hasn't been designed to be used at these frequencies. Matching is only -8 dB at 15 GHz. S21 trace is also very clean and looks very reasonable indicating that the short, open, and load definitions are correct.

Calibration algorithms

Same measurement calibrated with different calibration algorithms.

Since I saved the raw uncalibrated measurements, I can do the calibration afterwards using different calibration algorithms. I set the ideal thru standard to be a 50-ohm line that is 65 ps long with linear attenuation of 0.1 dB at 4 GHz. This is a simple transmission line model that agrees reasonably well at low frequencies, but the loss and matching differ significantly at higher frequencies. The delay should match well over the whole frequency range.

The SOLT (Short-Open-Load-Thru) calibration algorithm is the default classic VNA calibration algorithm that can also be used with a three-receiver VNA. It requires that all the calibration standards are known accurately. Since the thru standard has errors in this case, the solved S-parameters also have errors. Even though the matching of the thru is -20 dB at 6 GHz, the errors it causes are well above the measurement capability of the VNA.

Unknown thru calibration is likely the best option when calibrating to the end of SMA connectors. It only requires short, open, and load standards to be known, while the thru standard can be completely unknown, as long as it's reciprocal (S12=S21). However, this method requires a four-receiver VNA to measure the switch terms. This measurement is not possible with a three-receiver VNA. When switch terms are known it reduces the number of equations that needs to be solved in calibration by two, allowing some calibration standard definitions to be relaxed.

EightTerm calibration is similar to SOLT, where all the calibration standards are assumed to be known, However, it also includes switch terms, creating an overdetermined system of linear equations. This system is solved least squares, making it a good choice if all calibration standards, including thru, are known to high accuracy.

Both unknown thru and EightTerm calibration are significantly more accurate than SOLT because they have less unknowns to solve for. The thru standard is usually not known with high accuracy in low-cost VNAs, and a four-receiver VNA capable of measuring switch terms is required for these more advanced calibration methods.

TRL calibration

TRL calibration kit and DUT. J1-J2 is thru, J3-J4 is line, J5-J6 is another line with different connector footprint for testing, and J7-J8 is a diode that can be measured with the TRL calibration.

One especially useful calibration algorithm is thru-reflect-line calibration. It requires a four receiver VNA, but it's also possible to use it as a second-stage calibration with three receiver VNA. As the name implies, calibration standard are not the usual short, open, and load. Instead they are two different length transmission lines and reflect. Transmission lines need to have the same propagation constant and optimally the length difference is 90 degrees. Transmission line parameters don't need to be known and reflect can also be unknown but should be identical in both ports.

This is very useful calibration algorithm for measuring devices on PCB, as it allows the VNA reference planes to be calibrated on the PCB right next to the component being measured. It also solves for the transmission line propagation constant and can be useful just for characterizing transmission lines without requiring any calibration standards.

TRL kit thru and line S-parameters calibrated to SMA connectors.

I first measured the lines using unknown thru calibration calibrated to the SMA connectors. This gives some indication on the loss and matching. If the connectors are too reflective it can result in inaccurate calibration as the reflections make it hard to measure the device, but this should be fine.

Some slight ripple is visible in the S11 and S22 measurements, especially above 11 GHz where the 3rd LO harmonic is used. The main reason for the ripple below 11 GHz is due to the measurement cable stability. If I'm not careful with keeping the cables stable the ripple can be even larger.

TRL kit thru and line S21 zoom.

Zooming into the S21 trace, it's very clean below 11 GHz. Above this frequency, the 3rd harmonic LO starts to be used resulting in significantly larger trace noise. Some of the trace noise at low frequencies can be caused by the calibration kit definitions that uses measurements instead of models. Any noise in the calibration kit measurement will be transferred to the measurements.

Time-domain impedance step response of the line.

Using Fourier transform, the time-domain impedance step response of the measurement can be obtained. In this case, calculating the time-domain response of the line shows the impedance discontinuities from the SMA connectors and it also gives an estimate for the transmission line impedance, about 50.5 ohms. The mathematical transformation from frequency to time-domain is much easier and accurate than trying to actually sample the reflected waveform at 15 GHz sampling frequency.

The quality of the time-domain transformed data is excellent. With my previous VNA the same measurement would be too inaccurate to be useful.

Transmission line parameters solved by the TRL calibration.

TRL calibration solves the transmission line propagation constant during the calibration. It's useful to plot this as effective permittivity and loss per cm. In this case reflect standard can be short calibration standard at the end of the coaxial cable and no separate reflect standard is needed on the PCB.

I also compared these values to microstrip line model using 4.6 substrate dielectric constant and 0.015 loss tangent. These should be about what they are supposed to be and it agrees somewhat okay. FR4 is notoriously frequency dependent material and the model using non-frequency dependent parameters doesn't match over the full frequency range. FR4 dielectric constant decreases and the loss tangent increases as the frequency increases.

This isn't quite ideal test setup for characterizing the transmission lines since the length difference between thru and line is just 9 mm. This small length difference leads to small differences in the S-parameters and makes the measurement sensitive to noise, measurement errors, and differences in the connector S-parameters. Especially with these low-cost SMA connectors I'm using there can be some small difference between thru and line SMA connectors, which cause errors in the solved transmission line parameters. I don't think the peak at 9 GHz for example is caused by VNA measurement accuracy, and it's more likely to be due to differences in the SMA connector S-parameters. FR4 substrate also isn't uniform due to fiberglass wave construction and two identical lines at different places in the weave can have slight differences.

Repeatability also impacts the accuracy of TRL calibration. This TRL kit was designed for frequencies up to 6 GHz, and the solved transmission line parameters remain accurate up to that frequency. The TRL calibration should also maintain its accuracy up to this frequency. Beyond that the calibration is likely not as accurate.

Varactor diode measurement

Varactor diode measurement setup.

With the TRL calibration it's possible to calibrate the VNA right next to the component being measured on the PCB. This allows accurately characterizing SMD components.

The varactor diode on the PCB is SMV2020-079LF. It's a diode whose capacitance changes as the reverse bias voltage across the diode is varied. They are used, for example, in voltage-controlled oscillators.

Normalized standard deviation of the TRL calibration.

TRL calibration accuracy depends on the phase shift between thru and line standards. It's best when the phase shift is ±90 degrees and extremely poor when the phase shift is 0 or 180 degrees. The theoretical effect on calibration results can be quantified by calculating the normalized standard deviation of the noise in result, normalized to the best case of 90-degree phase shift. In this case, the best accuracy is around 4.6 GHz, and poorest at 9 GHz due to the line length being 180 degrees at that frequency.

I didn't have this good VNA when I made this PCB, so I didn't think to include a second shorter line to extend the calibration maximum frequency. With this TRL kit, measurement accuracy will be poor around 9 GHz.

Bias-T's added to VNA ports for biasing the diode.

To measure the diode S-parameters at different bias voltages, I added bias-T's to both VNA ports. Adding them close to VNA is better for stability, and taping down the SMA cables minimizes their movement during measurement, improving stability.

S-parameters of the diode with 0V bias with TRL calibration.

9 GHz calibration singularity severely affects the results, but the S-parameters are clean before and after it. TRL calibration accuracy is also poor at low frequencies, but due to higher SNR, better stability, and better connector repeatability at low frequencies, it doesn't cause similar issues.

Diode S21 and S11 measurements at 0 - 20 V reverse voltage.

I measured the diode at 0 to 20 V reverse bias voltage in 1 V increments. The frequency range is limited to 7 GHz to avoid the calibration singularity. The diode is expected to behave like a variable capacitor, with capacitance being the largest at zero bias and decreasing as the reverse bias increases.

This measurement would have requires flipping the DUT after every measurement if I was using a 1.5-receiver VNA. It would have not only been very tedious, but also terrible for measurement accuracy. However, with a proper two-port VNA, the measurement setup can remain static and making the measurement is very quick only taking few minutes.

Measurement vs SPICE model at 10 V reverse bias.

The diode has a manufacturer supplied SPICE model. Comparing the measurements to it, the results are quite close at low frequencies but some differences in S11 and S22 can be seen at higher frequencies.

The results can be expected to be at least a little different since my measurement includes PCB pads which are not included in the SPICE model.

Capacitance vs reverse voltage. My measurement result vs datasheet plot.

When a capacitor is fitted to the measured S-parameters, the capacitance vs reverse voltage graph is very similar to that on the datasheet. However, in my measurement, the diode has few hundred femtofarad higher capacitance at low bias. Some of this discrepancy could be caused by the PCB and it's also possible that there is some manufacturing variation in the diodes.

The diode measurement results have very low noise and the VNA can measure the diodes low capacitance very accurately.

Conclusion

Schematic of the VNA (click to open).

The designed VNA has excellent measurement quality, easily surpassing all of the existing low-cost VNAs. It has four receivers which makes advanced calibration methods, such as unknown thru possible. Isolation is excellent, over 120 dB, and the source frequency range is 10 MHz to 15 GHz.

The total cost of components in prototype quantities was $300, PCBs cost $100 for five pieces, and the CNC machined case was $75 (excluding taxes and shipping). The couplers require some manual assembly, but it should be possible to manufacture this at very low cost. I don't have plans at the moment to manufacture these for sale. The schematic of the VNA is available above for anyone interested in making their own VNA or just curious about the details.

Homemade polarimetric synthetic aperture radar drone

2025-02-11T00:00:00+02:00

Introduction

Radar drone ready to take off from snow.

I have made several homebuilt radars and done some synthetic aperture imaging testing with them on the ground. I have wanted for a long time to put a radar on
a drone and capture synthetic aperture images from air. When I last looked at this few years ago, medium sized drones with payload capability were around 1,000 EUR and up. For example in Low-Cost, High-Resolution, Drone-Borne SAR Imaging paper by A. Bekar, M. Antoniou and C. J. Baker, the imaging results look excellent. They used DJI S900 drone with a list price of about 1,000 EUR. The price for the whole system is quoted to be £15,000, which is a way too high for my personal budget even just for the price of the drone. Many other papers use similar style medium sized drones designed for carrying cameras and they are usually equipped with RTK-GPS for accurate positioning.

One of many cheap Chinese FPV kits.

Recently small FPV drone prices have dropped a lot. Small 5 and 7 inch propeller quadcopters can be bought for about 100 EUR from China (not including battery and RC controller). Despite their small size they are able to lift about 1 kg or even heavier payload which is plenty for a small radar.

I bought the cheapest Chinese no-name 7-inch FPV kit and a small GPS+compass module to support autonomous flying with the goal of making a light weight synthetic aperture radar system that it can carry.

Synthetic aperture imaging

A single-channel radar can only measure the distance to a target and is unable to detect the angle of the target. When multiple receiver channels are arranged in a line, the signal travels slightly different distances to each receiver based on the target's angle, causing phase shifts in the received signals. These phase shifts allows calculating the angle of the target.

Angular resolution ($\Delta \theta$) of antenna depends on its size approximately as: $\Delta \theta \approx \lambda/D$, where $\lambda$ is the wavelength, and $D$ is the diameter of the antenna. For example to have 1 m resolution at 1 km distance requires 0.03° angular resolution with 6 GHz RF frequency. This would require antenna size to be about 100 meters.

Instead of making a single large antenna, it's possible to move a single radar and take multiple measurements at different positions. If the scene remains static, this approach yields the same results as having one many channel radar system with big antenna. With synthetic aperture radar it's possible to attach a single-channel radar to a drone, fly it while making measurements, creating a large synthetic aperture that provides exceptional angular resolution.

Radar design

Dimensions of the drone frame. (3d model source)

The design goal for the radar is to get the best imaging performance while being able to fit into the FPV drone and achieving it with minimal budget (<500 EUR). The budget limitation rules out using any low-loss RF materials and both electronics and antennas should be implemented with lossy FR4 PCB material.

The drone is quite small and this limits the maximum size of the radar. The width of the frame is about 40 mm and propeller tip-to-tip distance is 50 mm across the frame. Length is about 170 mm, which is much more than width and means that ideally the radar is skinny. For example Raspberry Pi is 56 x 85 mm which is too wide. The small size severely limits on what the radar can include.

Block diagrams of FMCW (left) and pulse radar (right).

There are several possible architectures for the radar. I previously made pulse radar that is about 64 x 132 mm. That's little too wide for the drone, but I believe it would be possible to shrink it a little. Issue with that radar is that the maximum bandwidth is about 100 MHz and it's limited by the ADC sampling rate. This corresponds to a range resolution of 1.5 m, which isn't quite high enough for a detailed image. It's hard to get much larger ADC bandwidth on a reasonable budget and fitting high speed ADCs on the limited space is also an issue. There's also a variation of pulse radar that has two ramp generators, one for RX and one for TX. This results in low frequency IF signal like with FMCW radar. This is an architecture that is often used on SAR radars as it allows for high RF bandwidth without requiring high speed ADC.

Since pulse radar with switched antenna can't transmit and receive at the same time, pulsed radar maximum pulse length is limited by the time it takes for the pulse to travel to the target and back. With for example 100 m minimum distance, the maximum pulse length to not miss any part of the pulse is only 670 ns. Because pulse radar needs to divide measurement time between transmission and reception it reduces the average transmit power and decreases the signal-to-noise ratio. Large number of very short pulses also complicates the image formation. Time taken by the SAR image formation scales with the number of pulses and very short maximum pulse length requires transmitting very large number of them for a good SNR image.

FMCW radar can transmit and receive at the same time and which improves the signal-to-noise ratio. The maximum sweep length is only limited by the synthetic aperture sampling speed requirements but it can be hundreds of µs. Unlike pulse radar, there is also a minimum sweep length requirement, since reflected signal is mixed to the transmitted signal it needs to be received while the sweep is still being transmitted. Long sweep length allows collecting much more reflected power per one sweep. Pulse radar could also use separate TX and RX antennas so that this wouldn't be an issue, but that removes its advantages compared to cheaper to implement FMCW radar. Separate transmit and receive antennas require more space, but due to large maximum length it should be possible to fit two small antennas side-by-side under the drone.

In general FMCW radar has advantage for short range and slow moving platform applications. Pulse radar is required when long range (more than few km) is needed.

RF design

FMCW radar architecture.

Above is the block diagram of the RF parts of the FMCW radar with dual-polarized antennas. The sweep is generated by PLL, it's passed through a variable attenuator and then amplified by the power amplifier. Most of it is passed to the transmit antenna, polarization switch controls whether vertically or horizontally polarized antenna is used. Part of the transmitted signal is coupled to the receiver mixer, where it's mixed together with the received reflected signal that has been amplified by the LNA. Receiver also has a polarization switch, together with the transmit switch it allows the radar to receiver and transmit any of the four combinations of polarizations. The mixer outputs a low frequency signal that is amplified and then digitized by the ADC. Some filtering is needed in the receiver to avoid large out of band signals and ADC aliasing.

DAC or DDS based sweep generation would likely be better than PLL. DDS phase noise is often better and it can change frequencies essentially instantly compared to PLL, but PLL is chosen because it's cheaper and requires less space.

RF frequency is going to be around 6 GHz as this is the maximum frequency where there are many cheap RF components for consumer applications. The highest output power cheap power amplifiers at this frequency output around 30 dBm. Low noise amplifiers for the receiver with 1 - 2 dB noise figure can also be obtained cheaply.

Receiver is direct conversion architecture and the mixer does not have any image rejection. This causes both frequencies above and below the transmitted signal to be converted to the same output frequency. This is not ideal as noise below and above the instantaneous sweep frequency is received increasing the noise floor by 3 dB. IQ sampling receiver that could reject the other sideband would need two mixers and ADCs. For only 3 dB increase in the signal to noise ratio, I didn't think it was worth the cost and PCB space.

Polarization switches allow choosing which polarization is used to transmit and receive. H is horizontal and V is vertical polarization. This allows measuring four polarizations: HH, HV, VH and VV, where the first letter denotes TX polarization and the second RX. Some targets reflect some polarizations more than others and it is used in remote sensing to determine properties of reflected targets. For example many smooth targets often reflect the same polarization with shape of the target determining if it reflects more HH or VV components. Forest and vegetation usually has higher cross-polarized HV and VH component reflection compared to roads and bare ground due to multiple reflections inside the vegetation.

Although H and V antennas are drawn separately in the block diagram, this doesn't mean that the system requires four antennas. It's possible to design antenna with two ports, one which radiates H and the other V polarization. Dual polarized antenna doesn't necessarily need any more space than single polarized antenna.

It would be possible to receive both H and V at the same time if the radar would have two receivers. This would have some advantages, it would allow removing the RX polarization switch which would decrease the losses and only the TX should be switched allowing more time for each measurement which would also increase SNR. It would also allow transmitting sweeps faster as there isn't need to multiplex the receiver polarization switch. However, I didn't consider it being worth the cost.

TX-RX leakage

TX-RX leakage can saturate the receiver on high powered FMCW radar if the leakage is too high.

More RF power generally improves the signal-to-noise ratio, but since FMCW radar transmits and receives at the same time, it's important to consider the TX-RX leakage signal. The receiver must be sensitive enough to be able to detect the thermal noise floor at -174 dBm/Hz without saturating due to leaked RF power from the transmitter antenna. Typical maximum input power that saturates the LNA is around -20 dBm. With +30 dBm transmitted power more than 50 dB isolation is needed between transmitter and receiver to prevent the receiver saturation. Even more isolation might be required if some other receiver component, such as ADC, saturates first. The variable attenuator before PA can be used to decrease the transmit power in case high enough isolation antennas don't fit in the drone. It also affects the receiver mixer's LO power, but mixers LO input power range should be large enough for it to not be an issue.

Link budget

The equation for the received power at the receiver input can be written as:

$$P_r = \frac{P_t G^2 \lambda^2 \sigma}{(4\pi)^3 r^4}$$

where $P_t$ is the transmitter power, $G$ is the antenna gain, $\lambda$ is wavelength, $\sigma$ is radar cross section of the target, and $r$ is range to the target. This is the received power from one pulse. Synthetic aperture is formed by sending multiple pulses while moving and these can all be coherently summed together to increase the signal to noise ratio. If image is formed from $n$ pulses, the received power can be multiplied by $n$ to get the received power in the whole image.

Radar measures radial distance δr, which is different from the ground resolution δx. δp is length of the area perpendicular to the antenna beam.

For a patch of ground, the reflectivity can be defined as: $\sigma = \sigma_0 A$, where $\sigma_0$ is reflectivity per unit area and $A = \delta x \delta y$ is the area of the ground patch. $\delta x$ is the resolution in the X-direction and $\delta y$ is resolution in cross-range direction. The radar measures radial distance $\delta r = \delta x \cos \alpha$, which causes the ground resolution to depend on the grazing angle $\alpha = \sin{h/r}$, with $h$ being the radar's height above the ground.

In this case $\delta x \approx \delta y \approx 0.3 m$, depending on the radar parameters, range, and imaging geometry. Reflectivity of the ground patch depends on the material of the ground patch and the angle of illumination. Reflectivity of ground is generally higher when it's illuminated at 90 degree angle (in direction of the ground normal vector). This causes the specular reflection to reflect back to the radar. At smaller angles there is still some reflection back to the radar, but it decreases as the incidence angle decreases. Typical ground reflectivity is around -20 to 0 dBsm (decibels square meter) with moderate look angle. At very low incidence angle there is additional problems with shadowing as there won't be any return from a target that radar doesn't have an unobstructed line of sight.

The minimum detectable power is limited by thermal noise of the receiver. It can be written as $kTBF$, where $k$ is Boltzmann constant, $T$ is receiver temperature, $B$ is the noise bandwidth and $F$ is noise figure of the receiver. It's a common mistake to confuse the noise bandwidth $B$ with RF bandwidth, but they are not related to each other. Noise bandwidth is the minimum bandwidth where receiver can separate noise and signal from each other. By taking Fourier transform of the input signal, we can discard all the frequency bins that are beyond the signal we are currently looking at, and noise at those discarded frequencies won't affect the detection capabilities of the receiver. FFT resolution resolution is equal to $1/t_s$, where $t_s$ is the sweep length.

Setting the received power $P_r$ equal to noise power and solving for $\sigma_0$ we get noise equivalent sigma zero (NESZ) that is value often used for comparing synthetic aperture radars.

$$ \text{NESZ} = \frac{(4 \pi)^3 r^4 k F T \cos \alpha}{n \delta x \delta y G^2 \lambda^2 P_t t_s} $$

The number of pulses in image $n$ could also be written as $t_m \text{PRF}$, where $t_m$ is the measurement time and $\text{PRF}$ is pulse repetition frequency. Or equivalently $l_m \text{PRF} / v$, where $l_m$ is the length of the flown track, and $v$ is the velocity of the drone during measurement. If the antenna points at a constant angle during measurement (stripmap image) the number of pulses in the image depends on the time that ground patch is illuminated by the antenna beam and can be much smaller than the previous number if the antenna beam is narrow. Quadcopter can easily fly pointing in arbitrary angle and it's possible to constantly point the antenna at the target (spotlight imaging) and this limitation doesn't necessarily apply in this case.

Variable	Explanation	Value
$P_t$	Transmitted power	30 dBm
$G$	Antenna gain	10 dBi
$\lambda$	Wavelength	5.2 cm
$\delta x \delta y$	Image pixel resolution	0.3 x 0.3 m
$T$	Receiver temperature	290 K
$t_s$	Pulse length	200 µs
$n$	Number of pulses in image	10000
$F$	Receiver noise figure	6 dB
$\alpha$	Grazing angle	30 deg

Noise equivalent sigma zero vs range with above listed parameters.

Plotting the NESZ as a function of range gives the above plot. There are some parameters that can be adjusted, mainly sweep length and the number of sweeps in image to slightly improve this figure. The requires NESZ for good quality image depends on the actual reflectivity of the ground, but typically for satellite based SAR NESZ is around -20 dBsm. With these parameters we should expect to see to around 1 - 2 km with ok image quality. This is slightly optimistic for drone SAR since 30 degree grazing angle at 2 km distance would require flying at 1 km altitude, which is much higher than is practical.

Pulse repetition frequency

Minimum alias-free pulse repetition frequency with 6 GHz RF frequency and with different number of time-multiplexed channels.

Radar image formation relies on the phase information of the received signal. If we consider a target that is 90 degrees from the antenna beam center (in the direction of movement) to avoid phase ambiguity, the maximum phase difference between two adjacent measurements needs to be less than 180 degrees. If the movement is larger than this, there can be multiple targets at different azimuth angles that have the same phase difference between measurements causing them to overlap in the image. Since both transmitter and receiver antennas move, a distance of a quarter wavelength between two measurements of the same target results in a half-wavelength difference in the distance traveled by the signal and a half-wavelength distance difference corresponds to 180-degree phase difference. At this spacing, targets at ±90 degrees will have the same 180-degree phase difference between measurements. If the measurement spacing is increased further more of the image starts to alias.

If the antenna is very directive then it's possible to use larger measurement spacing. Directive antenna won't radiate to large angles that would alias, and the more directive the antenna is, the larger the measurement spacing can be. However, since the drone is space-limited and antenna directivity is related to its size, it might not be possible to design a very directive antenna causing the maximum measurement spacing to be around quarter wavelength.

The common flying speed for a quadcopter is around 10 m/s, but flying speed can easily be decreased if needed. With 6 GHz RF frequency, the quarter wavelength is 12.5 mm (0.5 inches) and 10 m/s flying speed means that pulse repetition frequency needs to be at least 800 Hz. Since we have time multiplexed four different polarizations, we need to be able to measure all of them in this time.

PRF sets the requirement for maximum sweep length. With 4 * 800 Hz = 3.2 kHz PRF requirement this leaves maximum of 312.5 µs per sweep. However, some time needs to be reserved for time between sweeps due to limited locking time of the PLL. The locking time of the PLL is around 20 - 30 µs, leaving 280 µs for the maximum sweep length.

Required ADC sampling frequency

Required ADC sampling rate vs maximum range and RF bandwidth for FMCW radar with 250 µs sweep length.

FMCW radar mixes the received signal with a copy of the transmitted sweep, resulting in a sine wave signal at the mixer output with frequency depending on the range to the target. If the target is at distance $r$, the IF frequency $f$ can be calculated as: $f = \frac{2 B r}{c t_s}$, where $B$ is the bandwidth of the RF sweep, $c$ is the speed of light, and $t_s$ is the sweep length. The range resolution depends on the RF bandwidth $B$ as $\Delta r = \frac{c}{2B}$. For example, 150 MHz bandwidth is required for 1 m resolution, and 300 MHz bandwidth results in 0.5 m resolution.

If we have 300 MHz of RF bandwidth (0.5 m range resolution) and $t_s$ is 280 µs as calculated earlier, then we can calculate the required ADC sampling speed given the maximum target range we want to detect. For example, with 2 km maximum range, the IF signal frequency is 14 MHz. The ADC sampling frequency needs to be at least double this due to Nyquist sampling requirement, and some additional margin is needed for the anti-alias filter roll-off. This results in a minimum ADC sampling frequency of about 35 MHz. I chose to use 50 MHz sampling frequency.

FPGA

Block diagram of digital parts.

The amount of data and strict timing requirements of the sweep generation make it difficult to handle with microcontroller and FPGA is necessary. Microcontroller is useful for more complicated tasks such as communication with the drone flight controller and ground station, configuring the radar, and writing the data to a filesystem. I decided to use Zynq 7020 FPGA, the same one I used in my previous pulse radar. It has FPGA fabric and a dual-core ARM processor in the same package. This FPGA is nominally 150 EUR from ordinary distributors, but is available for fraction of that from Chinese distributors.

The drawback of this FPGA is that the microcontroller doesn't have many high speed connections. For example SD-card and EMMC interfaces are limited to 25 MB/s, which is below the data rate of the ADC. It does have 1 Gbps Ethernet, but using that would require adding a Raspberry Pi or similar computer, which isn't possible due to size constraints. For instance, newer Ultrascale+ FPGAs support SD-cards with 52 MB/s and EMMC at 200 MB/s speeds, but they cost around 500 EUR and are not available from Chinese low cost distributors.

Zynq can have external DDR3 DRAM, but due to space limitations, it's not possible to fit enough DRAM to store the whole measurement in memory. With limitation of only one DDR3 module, the memory is limited to 1 GB, while size of the measurement can be several gigabytes.

This leaves only the option of implementing fast enough external communication interface in the programmable logic side of the FPGA. Luckily Dan Gisselquist (ZipCPU) has made GPL3-licensed SD-card and EMMC controller that supports faster high-speed communication modes than the hard IP included with the ARM processor.

At the time, sdspi controller hadn't been tested with real hardware at the speeds I required. To make sure I have something working if I'm unable to get the sdspi core working I connected the SD-card to the ARM processor's integrated controller, which is limited to 25 MB/s, and EMMC memory to the programmable logic side that is used with the sdspi controller. This way I'm able to at least use the SD-card with the integrated controller if the sdspi core isn't suitable, but this turned out to be unnecessary and the sdspi controller worked fine. In future versions, it would be better to also connect the SD-card to PL side using sdspi core for faster SD-card speeds.

I also added FT600 USB3 bridge IC that can be used to connect FPGA to PC. This is not needed for drone usage, but allows real-time connection to PC for other applications.

FPGA program block diagram.

FPGA functionality is quite simple at the block diagram level. The design primarily consists of a few independent blocks wired with either DMA or AXI bus to the processor. For radar operation, the radar timer block is important as it switches internal and external signals during the measurement. It needs to be implemented in the FPGA fabric to ensure that the timing is clock cycle accurate to achieve phase-stable radar measurements. AXI bus is memory-mapped on the processor side, allowing the radar to be controlled by writing values to fixed memory addresses.

A decimating FIR filter after ADC data input can be used to change the sample rate of the ADC data. It can decimate by 1, 2, or 4. For long-range measurements, the decimation should be disabled for the maximum IF bandwidth. But for shorter-range measurements it makes sense to use higher decimation value to decrease the amount of data that needs to be stored.

PCB

Labeled PCB 3D model in KiCad. Some 3D models are missing.

The PCB has six layers and is designed to be as compact as possible, with components placed closely together to minimize size. Since one-sided assembly is cheaper than assembling both sides, the bottom side is empty except for one SD-card connector that I will solder myself.

As with many of my previous radars, the RF part is a relatively small part of the PCB and the overall design effort. Digital electronics and voltage regulators take up the majority of the PCB space.

Assembled PCB.

The radar is designed to accept input voltage from 12 to 30 V and connect directly to the drone's battery eliminating the need for an external DC/DC regulator.

Due to space constraints, there wasn't enough space to fit four SMA connectors and I didn't want to use any miniature RF connectors. The top two connectors are switchable TX outputs for H and V polarization antenna inputs, while the bottom third one is RX input. The RX polarization switch is located on an external PCB and connects to one of the three four-pin JST connectors on the bottom right of the PCB. Another JST connectors is for flight controller's serial port, and the third connector is currently unused, but it could be used to connect for example GPS.

There are two USB-C connectors: one for JTAG programming and debugging of the FPGA, and the other connects to USB3 to FIFO bridge chip that enables fast data transfer to PC. It isn't needed in drone use, but it's useful for testing and other applications.

PCB dimensions are 113 x 48 mm. Width is just skinny enough to fit on the drone, while it could have been slightly longer.

This component is not sale for individuals.

After ordering the PCB I made an order for the components from Mouser. The order seemed to succeed fine and they accepted my money but I got the above email afterwards telling me that they can't sell me one of the components. Reason seems to be that the supplier of the component has forbidden them for selling it to individuals. This was very frustrating as there was absolutely no warnings on the website and I had already ordered the PCBs. I was unable to order this component from anywhere, but I did find older obsolete PE43204 pin compatible IC from obsolete component reseller. It's specified only for maximum of 4 GHz when the original was up to 6 GHz but it does seems to have low enough loss at 6 GHz to not cause too large issues.

After asking on reddit the reason is probably that the manufacturer of the component wants to know who they are selling to, to avoid their components ending up in defense applications. That's fine, but it would have been nice to know that in advance.

SD-card interposer PCB.

I did make one mistake: SD-card pins are connected to 1.8 V I/O pins, while they should be connected to 3.3 V I/O and SD-card didn't work with this lower voltage. The radar could be used without SD-card by storing the data into EMMC instead and then reading it through USB, but SD-card would be much easier to use. I really didn't want to order another PCB to just fix this one mistake and I managed to fix it by designing a small interposer PCB with level shifter that I soldered on top of the previous SD-card footprint. I wrote about it in more detail in a previous post.

Aluminium PCB heatsink under the radar PCB.

Power amplifier can get quite hot if the transmit duty cycle is high. To keep it cool I ordered custom aluminium substrate PCB that I bolted under the radar PCB. Solder mask is removed under the PA and thermal pad is placed between the PCB and heatsink. This cost only $4 for 5 pieces and works very well.

Drone electronics

Speedybee F405 V3 flight controller.

Flight controller came with the drone kit. The included flight controller is Speedybee F405 V3. This is a cheap low-end flight controller with 1 MB of flash. It does the job, but I would recommend getting a little bit better flight controller with 2 MB of flash, the price difference isn't very large.

There are several possible flight controller softwares. The three most used for FPV drones are: Betaflight, Inav, and ArduPilot. The main differences of them are: Betaflight focuses on fast-response manual flying and doesn't have autonomous flight support, Inav shares lot of code with Betaflight and it includes some autonomous flight support, and ArduPilot has the most advanced autonomous flight capability with lot of features but it's more challenging to configure.

I chose to use Ardupilot and found it to be excellent for this purpose. It has very good IMU and GPS sensor fusion algorithm that is very helpful for improving the position accuracy. The flight controller can communicate with the radar through a serial port allowing it to enable and disable the radar during autonomous mission and provide position information for the radar.

GPS with integrated compass. It needs to be mounted far away from the battery leads to avoid magnetic fields causing issues with the compass.

SAR imaging needs very accurate position information for proper image focusing. Position information should be accurate within to a fraction of wavelength, this is just few cm (1 - 2 inches) at this frequency. Many commercial SAR imaging drones use RTK GPS with a second stationary GPS receiver on the ground it's possible to obtain about 1 cm accurate positioning. The drawback is that it's much more costly than regular GPS and RTK GPS receivers are usually much larger than ordinary GPS receivers which makes it very difficult to fit it in this drone.

Good non-RTK GPS might be accurate to about 1 m accuracy. This large positioning errors cause significant errors in the image if not corrected. Luckily, it's possible to solve for position error from the radar data which is called autofocusing. With drawback of needing more processing during the image formation for autofocusing, it's possible to use regular GPS. Sensor fusion with inertial measurement unit (IMU) can be used to improve accuracy of the positioning and obtain position updates faster than the maximum of about 4 Hz that is possible with only GPS.

For autonomous flying the drone's flight computer also needs GPS, IMU and compass. It would be a waste of space to have a second GPS and IMU for just the radar and instead I'm relying on the flight computer to output its position estimate to the radar through a serial interface.

Drone block diagram.

The drone is controlled with a radio controller. I use ExpressLRS radio link, which is very common with FPV drones. The drone also has a radio link to the ground control software running on PC. This is needed for programming the autonomous mission parameters, changing drone settings, it can be used to control the drone, and it displays telemetry during the flight. Ground station can also be used to send messages to radar through the flight controller and this allows programming the radar parameters from the laptop.

Typically Ardupilot has required using two radios. One for radio controller and other for telemetry, but ELRS recently added Mavlink support that allows using a single radio for both purposes. This is very convenient in this application.

Antennas

In theory, the wider the antenna beam width is, the better the resolution of SAR image is. A famous result in SAR imaging is that the best possible cross-range resolution in strip mode SAR (fixed antenna angle and straight baseline) is $L/2$, where $L$ is the length of the antenna. However, in practice wider antenna beam isn't often better. Wider antenna beam means lower gain which decreases the signal to noise ratio and limits the maximum range. Antenna gain is squared in the link budget so halving the antenna gain, means that number of pulses need to be quadrupled to get the same SNR.

The cross-range resolution depends on the length of the baseline where the target is visible and the wider the antenna beam is the longer this is. With spotlight imaging, where antenna tracks the target, cross-range resolution is not limited by the antenna beam width and spotlight imaging is easy with drone. With drone SAR the maximum possible baseline length is often the limiting factor for resolution as it's hard to fly very long track when limited by visual line of sight.

The azimuth angle resolution in spotlight imaging mode (or in stripmap mode where antenna beam always covers the target) can be approximated as: $\Delta \theta \approx \lambda/L$, where $\lambda$ is wavelength and $L$ is the length of the track. Cross-range resolution can be obtained with: $\Delta y = 2r \sin(\Delta \theta/2)$, where $r$ is distance to the target.

With drone SAR a big issue is how to fit large enough antennas on the drone. Since the radar is FMCW, separate transmitter and receiver antennas are needed further decreasing the space per antenna and low TX-RX leakage requires having some distance between them.

I have previously used self-made horn antennas with my radars, but they are too big to fit on drone. The whole length of the horn antenna is 100 mm, and even just the coaxial-to-waveguide transition is 25 mm long. This size makes it impossible to fit on the drone, which has only 50 mm spacing between propeller tips. My previous horn antenna isn't dual-polarized, but horn can be made dual-polarized easily by adding two feeds 90 degree apart.

Patch antenna can be made much smaller since they are just copper on a PCB. They can also be made dual-polarized with two feeds 90 degree apart. However, a simple patch on 1.6 mm thick FR4 PCB has poor bandwidth, FR4 dielectric inaccuracy can cause frequency shift, and the gain isn't very high. Gain can be improved by making an array of patches, but with FR4 substrate the losses in feeding network increase quickly.

Stacked aperture coupled patch antenna. Side (left) and top (right) views.

Neither horn nor patch antenna seemed suitable. After reading some scientific papers I found this dual-polarized slot-fed stacked patch antenna paper. It consists of patch antenna that is fed by microstrip lines that couple to patch through H-shaped slots in the ground plane. Two feed lines and slots 90 degree apart can be used to make it dual-polarized. A second patch is suspended few mm away from the first patch with air in between them. This structure can achieve much wider bandwidth than a single patch making it tolerant to frequency shift caused by inaccuracy of FR4 permittivity. The second patch also slightly increases the gain.

TX and RX patch fed horn antennas.

However, more gain would be good to have for improving the signal-to-noise ratio. Sidelobes at 90 degree angle should also be lower to decrease TX-RX leakage. To solve this I added a sheet metal horn structure around the antenna, making it a stacked patch fed horn antenna. The horn increases the height by 10 mm, but even just a sheet metal wrapped around the patch gap increases the gain and decreases sidelobes without increasing the height. I haven't found a similar structure in any publications, but it wouldn't surprise me if some exist, as it does seem straightforward.

A pyramidal horn with filled-in corners would likely offer slightly higher gain and be mechanically stiffer than this four-flap design. However, this was easier for me to manufacture. I cut the copper sheet by hand with scissors and soldered it to keep it together.

This antenna has everything I wanted. It's dual-polarized, has very wide bandwidth, good gain, isn't as tall as similar gain horn antenna fed with coaxial-to-waveguide transition, and it's cheap to manufacture requiring just two FR4 PCBs, some copper sheet and few bolts and spacers. FR4 is lossy and gain would likely be around 0.5 - 1.0 dB higher if a proper low loss RF material was used, but the cost would be about 100x higher in prototype quantities and it doesn't make sense for me to spend so much more for so little improvement.

Between the antennas is a small 0.25 x 0.5 wavelength wall that decreases TX-RX coupling. I tested few different size walls and this small wall is more effective than no wall and also more effective than taller walls.

Not counting the SMA connectors, the height of the antenna is 18 mm, of which 10 mm is the height of the horn above the suspended patch. Total height including the SMA connector is 28 mm. Patch substrate dimension is 45 x 45 mm and the horn aperture is 65 x 65 mm.

Backside of the antennas. Each antenna has two SMA connectors, one for H and other for V polarization.

Backside of the antennas is covered by copper sheet to decrease the backwards radiation. This is needed because antennas are mounted right on top of the radar PCB which doesn't have any shielding. Without shielding TX antenna backwards radiation would increase the TX-RX coupling. Copper sheet is also inserted into the wall between antennas and the tape keeps it in place.

Simulated radiation pattern of the antenna.

The simulated -3 dB beamwidth is 50/60 degrees in 0/90 degree angles. H and V feed slots are rotated 90 degrees and the radiation pattern from the other port is similar but rotated 90 degrees. Simulated peak gain is 10.0 dB.

Sidelobe to 90 degree direction is about -10 dB. It's important for this to be low to minimize TX-RX leakage.

Since the antenna radiation pattern isn't quite symmetrical, mounting the other antenna at a 90-degree rotation compared to the first one ensures good antenna pattern matching between HH and VV polarizations. If the TX antenna transmits H polarization from the first port, RX antenna receives H polarization from the other port, and other way around for V, causing the two-way antenna pattern to match between the both cases. However, HV and VH antenna patterns don't match the HH and VV patterns, since in the cross-polarization case the same port is used to transmit and receive on both antennas.

Measured S-parameters of the antenna.

There is a slight difference in the H and V port matching due to their slightly different coupling slot sizes. Antenna useable bandwidth is from about 4.5 GHz to 6.2 GHz which is more than enough for this application.

Mechanical design

Drone mechanical model in Blender.

The drone needs some mechanical parts to hold the radar on the drone frame. The flight controller is mounted inside the frame, but there isn't enough room inside it for the radar, so I designed a 3D printed mount that holds the radar PCB under the drone frame. This mounting position also requires landing legs so that the drone doesn't land on the radar. I designed it in Blender since I don't know any mechanical CAD programs. It works just fine for these simple parts.

Radar attached under the drone.

The radar mount holds the radar PCB on the drone frame. It would be a good idea to have some sort of weather proof enclosure for it, but I haven't got around it yet. I added some material over the PCB to protect it in case the landing legs fail.

Radar holder attaches with four screws to the drone. Drone radio controller antenna is visible at the bottom left. Propellers are collapsible, these make it much easier to transport the drone as with these it fits in a backpack.

Receiver polarization switch PCB.

Antenna board is held with two bolts that allow its angle to be changed. Flight controller serial port is attached to one of the JST connectors. There also other JST connector from flight controller that is currently unused and just held with tape in place.

Transmitter has polarization switch and two SMA connectors on the PCB, but the receiver polarization switch is on a separate PCB due to lack of space. I had a mounting holes for it on the radar holder part, but the SMA cables are stiff enough that I found it easier to just leave it hanging there. Polarization switch connects to the radar PCB with another JST connector.

Drone with landing legs.

Landing legs are 10 cm diameter carbon tubes with 3D printed TPU caps. Smaller diameter tube would have likely been fine, these are very stiff and something else would fail before them if they are stressed too much in landing.

Radar is powered directly from the drone battery. XT60 splitter is used to connect both flight controller and radar to the same battery.

Drone balanced on a kitchen scale.

Weight of the drone without battery is just 752 grams (1.66 lbs). I have two six cell LiPo batteries, the smaller 1300 mAh capacity battery weights 196 grams and the bigger 2200 mAh battery weights 322 grams. With the smaller battery the total weight of the whole system is just 948 grams.

Image formation

Radar measures the distance and phase of each target. To convert these measurements into a radar image, matched filtering can be used. For each pixel in the image, generate a reference signal corresponding to what a target at that position would reflect. Multiply the measured signal with the complex conjugate of the reference signal for each measurement, then sum these products over all measurements. When the measured signal closely matches the reference signal, their product becomes large because the phases align. If it doesn't match, the result of the multiplication is a complex number with a random phase, and summing random complex numbers will average out generating a low response.

The image formation can be written as:

$$I = \sum_{p \in \mathcal{P}} \sum_{n=1}^N S_n(d(p,x_n)) \cdot H(d(p,x_n))^* $$

, where $\mathcal{P}$ is the set of pixels in the image, $N$ is the number of radar measurements, $S_n$ is Fourier transformed measured IF signal $s_n$, $d(p,x_n)$ is the distance to location of pixel $p$ from radar position at that measurement $x_n$, and $H^*$ is complex conjugate of the reference function of what target at that position in the image should look like (Fourier transform of the radar IF signal from target at that position in the image).

This is called backprojection algorithm. It's simple and doesn't make any approximations or assumptions about flight geometry, but it's very demanding to calculate. For example with 1 km x 1 km image with 0.3 m resolution and 10,000 radar sweeps, calculating the image needs $(1000/0.3)^2 \cdot 10000 = 111 \cdot 10^9$ backprojections. This means over 100 billion complex exponentials and square root calculations is needed for one image, and image size and number of sweeps can be even larger in practice. There are some clever algorithms that can be used to speed this up, but they often have approximations or only work with linear flight tracks. One easy improvement that can be made without many drawbacks, is to use polar coordinates instead of Cartesian coordinates, as that requires less pixels in the image since angular resolution is constant while cross-range resolution is better closer to the radar. Polar coordinate image can then be afterwards interpolated to Cartesian grid.

__global__ void backprojection_polar_2d_kernel(
          const complex64_t* data, const float* pos, complex64_t* img,
          int sweep_samples, int nsweeps, float ref_phase,
          float delta_r, float r0, float dr, float theta0,
          float dtheta, int Nr, int Ntheta, float d0) {
    const int idx = blockIdx.x * blockDim.x + threadIdx.x;
    const int idtheta = idx % Ntheta;
    const int idr = idx / Ntheta;

    if (idr >= Nr || idtheta >= Ntheta) {
        return;
    }

    const float r = r0 + idr * dr;
    const float theta = theta0 + idtheta * dtheta;
    const float x = r * sqrtf(1.0f - theta*theta);
    const float y = r * theta;

    complex64_t pixel = {0.0f, 0.0f};

    for(int i = 0; i < nsweeps; i++) {
        // Sweep reference position.
        float pos_x = pos[idbatch * nsweeps * 3 + i * 3 + 0];
        float pos_y = pos[idbatch * nsweeps * 3 + i * 3 + 1];
        float pos_z = pos[idbatch * nsweeps * 3 + i * 3 + 2];
        float px = (x - pos_x);
        float py = (y - pos_y);
        float pz2 = pos_z * pos_z;

        // Calculate distance to the pixel.
        float drx = 2.0f * sqrtf(px * px + py * py + pz2) - d0;
        float sx = delta_r * d;

        // Linear interpolation.
        int id0 = sx;
        int id1 = id0 + 1;
        if (id0 < 0 || id1 >= sweep_samples) {
            continue;
        }
        complex64_t s0 = data[i * sweep_samples + id0];
        complex64_t s1 = data[i * sweep_samples + id1];

        float interp_idx = sx - id0;
        complex64_t s = (1.0f - interp_idx) * s0 + interp_idx * s1;

        float ref_sin, ref_cos;
        sincospif(ref_phase * d, &ref_sin, &ref_cos);
        complex64_t ref = {ref_cos, ref_sin};
        pixel += s * ref;
    }
    img[idr * Ntheta + idtheta] = pixel;
}

Some years ago this would have been unbelievable amount of compute, but with modern GPU this can be calculated in under a second. This problem is especially well suited for GPU implementation since every pixel can be calculated independently in parallel. Very straightforward CUDA kernel is able to calculate 220 Billion backprojections per second on RTX 3090 Ti GPU. This is very respectable speed considering that each backprojection requires square root and complex exponential (which can be calculated with just sin and cos). I'm sure that someone experienced with CUDA programming could make this even faster as this doesn't have any optimizations or approximations and is just the direct algorithm implementation.

Autofocus

Autofocus block diagram.

Positioning accuracy of the GPS and IMU isn't good enough to form a high-quality image. Ideally, the position should be known to a fraction of the wavelength, but accuracy of the GPS isn't good enough. To achieve good image quality, an autofocus algorithm is necessary to focus the radar image using information from the radar data.

The most commonly used autofocus algorithm is phase gradient autofocus. It's simple and fast autofocus algorithm that works by taking an unfocused radar image as an input and solving for a phase vector that when multiplied with the azimuth FFT of the image gives a focused image. However, it doesn't work well in this case since the azimuth beam is wide and the radar baseline is long causing the focusing errors to be spatially dependent.

I updated my previous backpropagation autofocus to use PyTorch and made some improvements. This autofocus algorithm works by forming the radar image, calculating the gradient of the input velocity, and clipping the learning rate to limit the maximum position change to a predefined value. The input velocity is then updated using a gradient descent optimizer. I found that using a 3D position doesn't work well, as it often tends to just nudge each position in random directions. Instead, using velocity and integrating it to position seems to yield much better results. A small regularization term is also included to minimize the distance between the optimized and original positions, favoring smaller updates.

Adjusting the learning rate based on the maximum position change makes it easier to set the optimizer meta parameters. Instead of setting the learning rate directly, maximum position update is given which is used to set the learning rate.

This is very general autofocus algorithm that makes no assumptions about the radar system, scene, or the flight track. The obvious disadvantage is that it requires forming the radar image many times making the already slow image formation many times slower. Without the fast GPU image formation this would be too slow to be useful.

The autofocus algorithm is available on Github.

Measurements

Configuring the mission in ArduPilot Mission Planner.

The mission is programmed beforehand with the ArduPilot Mission Planner. The drone will automatically fly the programmed waypoints, there are also commands to set the ROI (region of interest) so that antenna always points towards it, and the radar measurement is started with digicam configure command in the mission. It's originally meant for configuring ordinary camera, but I programmed the radar microcontroller to listen to it. Using an existing command makes it easy to make the radar work with the existing ArduPilot software.

Setting ROI, which is needed for spotlight imaging, needs a patch to ArduPilot firmware. By default drone's front will always point towards the ROI and there isn't a way to configure it to point the antenna towards ROI instead. The patch is available on the ArduPilot Github as a pull request.

Drone in action.

The scene is a wide open field. There's about 1.5 km distance to the forest at the antenna pointing direction. The drone flies at 110 m altitude in a straight line for about 500 m at 5 m/s velocity. The radar was configured to transmit only VV polarization with 400 µs long sweep, 500 MHz bandwidth, and 1 kHz pulse repetition frequency.

Range compressed raw data.

The range compressed (Fourier transformed) captured data doesn't look very impressive. It doesn't look anything like an image since due to the wide antenna beam at each sweep many targets at different angles are captured.

At the zero distance there is a large response from the TX-RX leakage, then the next reflection is at 100 m distance from the ground. Even though the antenna gain at directly below is much smaller than at the beam center, due to the angle of the reflection and close distance, the reflection from directly below is very large. At large distances reflections are mostly below the noise floor of individual sweeps, but during image formation many sweeps are integrated improving the signal to noise ratio. Some large individual objects are visible and their distance to the radar changes as the drone moves.

Recorded drone position and antenna pointing vector from GPS and IMU. Note the unequal axes scale.

Ideally the track should have been a straight line but there is some disturbances due to for example wind. The drone is very light and even a slight wind can easily affect it. The ROI was set quite far away there is only few degree of change in the antenna pointing direction during the measurement.

SAR image without autofocus.

Above is the processed SAR image without autofocus in pseudo-polar coordinates that the image formation uses internally. It's pseudo-polar because angle axis is in sine of radians instead of just radians, this is slightly more efficient than ordinary polar coordinates. Image size is 6k x 20k pixels using 51,200 sweeps.

Compared to the raw data it's a night and day. Various geographical features can be now identified, but polar format makes it hard to compare to the map.

SAR image without autofocus.

Cartesian coordinate image can be obtained by projecting the pseudo-polar image to Cartesian grid. This is very fast operation compared forming the image directly on the Cartesian grid. The image is also aligned so that north points up using the drone's electronic compass measurements. Left corner is missing a small patch of data due to the rotation.

The resulting image is still quite blurry. Clearly only relying on the GPS and IMU positioning isn't good enough and autofocus is needed to get a sharply focused image.

Autofocused SAR image.

After applying 30 iterations of the minimum entropy gradient optimization autofocus, the image quality is much better. Five iterations would have been probably enough, but using more iterations does improve the quality slightly. This does take several minutes since each iteration requires calculating forward and backwards pass of the backprojection.

Due to the low grazing angle, tall structures such as trees cast long shadows. The image amplitude isn't normalized, which is why it's brighter closer to the origin. The antenna radiation pattern can be also visualized in the image. The beam center is tilted slightly to the right, and the antenna gain at the left side of the image is much smaller due to it being farther from the beam center, causing it to be dimmer.

SAR image detail comparison. Without autofocus (left) and with minimum entropy optimization autofocus (right).

There is quite lot of detail in the resulting radar image when zooming in. Comparing a 300 x 300 m patch, the autofocused image reveals surface details of the field that was just blur in the image without autofocus.

I also tried using phase gradient autofocus, but it doesn't work well in this case. The result is very similar to the image without autofocus.

The three lines at the bottom left are power lines. They seem to be only visible in the image when the radar is looking at them at 90 degree angle, at other angles the reflectivity is so low that they are invisible.

Original and optimized velocity.

Comparing the drone velocity before and after optimization the changes aren't very large. Along the track and range direction velocity components are both adjusted slightly and height direction velocity component is basically unchanged.

Full polarization measurement

Google maps screenshot of the SAR imaging area.

I also made another measurement at other location using all four polarizations. The radar flies a linear track autonomously as before, but now the radar quickly switches between each of the four polarization switch states. Sweep length was reduced to 200 µs, pulse repetition frequency is 715 Hz for each polarization, and other parameters are kept the same. Number of sweeps in the image is the same 51,200.

Four SAR images with different polarizations.

The four polarizations look very similar. The main differences are that cross-polarization images (HV and VH) have weaker amplitude due to cross-polarization component in general being smaller than the reflection of the same polarization.

Polarized SAR image with autofocus.

Instead of looking at four different images for each polarization, it's common to use RGB color channels for different polarizations in the same image. In this colored image it's easier to visualize how each target reflects specific polarizations. The ground is tinted purple, indicating that it reflects VV and HH polarization better than the cross-polarized components. The same can be seen on the buildings and in the light poles along the road. Forest areas are colored white as they reflect all polarizations about equally. However, since the effects of the antenna radiation pattern and possibly slightly different losses for different polarization switch states are not calibrated some of the observed differences could be attributed to the hardware. Better accuracy measurements would require calibration.

The area with bunch of points around (200, 500) meters is a some kind of garden of small trees each surrounded with a metal wire mesh.

Picture at the ground at (-50, -80) m coordinates in the SAR image looking towards negative Y-axis.

There was slight amount of snow on the ground during the measurements. The visible picture is from the top of the SAR image looking down. The small forest on the left is the small patch of trees in the middle of the image.

VideoSAR

Drone waypoints for the octagonal flight path. Red marker is the region-of-interest where drone points the antenna.

The previous measurements synthesized one high-resolution image from a long baseline. It's also possible to synthesize many images with small baselines from one long measurement, and these many images can then be turned into a video.

For the backprojection algorithm, the flight track doesn't need to be linear and for this case I programmed the drone to fly octagonal track while pointing the antenna at the octagon's center.

Your browser does not support the video tag.

Each frame has 1024 radar sweeps with 512 of them overlapping with the previous frame. Since each frame has less sweeps than the previous full images, the frames are noisier and have worse angular resolution. The video is sped up by about 10x. All four polarizations are used, and the image colorization is the same as in the previous polarized SAR image.

Frames are autofocused separately and there isn't any alignment of adjacent frames, which causes the frames slightly wobble or jump around occasionally. Corners of the octagon are especially challenging for the image formation since both along- and cross-range positions need to be solved accurately for a good-quality image. Angular resolution can also vary between frames as the baseline length between the frames can vary, as only the number of sweeps is the same between the frames.

Natural targets such as the ground and forest look very similar at different frames, but at several points in the video large reflections can be seen for example at bridge and power lines when they are oriented at a 90-degree angle to the radar. The bright spot that looks like it's moving at the bridge is just glint from the railing. The mismatch between antenna patterns of different polarizations is also visible as the same target can have slightly different color at the beam center or at the edge.

Imaging geometry

Radar look angle with 120 m flying height.

Without special permits, it's allowed to fly the drone at a maximum altitude of 120 m. Usually, for SAR imaging, the look angle is around 10 to 50 degrees. If the look angle is close to 90 degrees (i.e., looking straight down at the ground), the reflected power is high, but the range resolution is poor as the distance to the radar is almost the same for nearby locations. For low look angles the range resolution is good, but due to the low grazing angle the reflected power back to the radar is low. With extremely low look angle the reflected power can be about 10 to 20 dB lower than it would be compared to more usual around 45 degree look angle reducing the maximum distance the radar can see.

Another issue is shadowing caused by tall objects. For instance, when flying at 120 m height, the grazing angle at 2 km distance is only 3.4 degrees. A 10 m tall tree casts 170 m long shadow at this low angle, making it impossible to see any reflections from the ground after the tall object. This is clearly visible in all of the measurements. Especially in the full-polarization measurement only the tops of the buildings are visible at long distances.

Update October 2025

Camera image of the scene.

SAR image of urban scene with new image processing software.

Since publishing this post, I have worked a lot on the image processing software and now I can generate much better quality images. For more details see the newer post: Synthetic aperture radar autofocus and calibration.

Conclusion

Schematic of the radar (click to open).

The synthetic aperture radar drone can image at least up to 1.5 km and likely even farther if flown higher. It weighs under 1 kg including the radar, drone, and battery. The system can capture HH, HV, VH, and VV polarizations. A gradient-based minimum entropy autofocus algorithm is capable of producing good good-quality images with a wide antenna beam using only non-RTK GPS and IMU sensor information. The total cost of the drone was about 200 EUR, 600 EUR for two radar PCBs, and about 10 months of my free-time after work. I'm very happy with the performance of the system considering its low cost.

Differentiable GPU image formation library is released on Github under MIT license. Schematic of the radar is also available above.

Fixing incorrectly wired SD card connector with interposer PCB

2024-08-02T00:00:00+03:00

Introduction

A while ago ordered a PCB where I made a mistake of connecting SD card to 1.8 V logic level I/O pins instead of the correct 3.3 V. As a result the SD card in that PCB didn't work. Otherwise the PCB was good and I didn't want to reorder the whole PCB to fix this one mistake as it would have cost over 500 EUR.

Bottom of the PCB and the incorrectly wired SD card connector pads.

I had placed the SD card connector on the bottom of the PCB without many components near it. The plan to fix it was to manufacture a small interposer PCB with 1.8 V to 3.3 V logic level translator, SD card connector, and matching pads on the bottom so that it can be soldered directly to the bigger PCB.

Example of commercially sold PCB with castellated holes meant to be directly soldered on bigger PCB.

Typically when soldering PCBs directly together castellated holes are used. They are plated holes that overlap the edge of the PCB such that half of the hole is routed out. This leaves nice plated edge to the PCB that is easy to solder.

However, the issue with using castellated holes in this case is that pitch of the SD card connector pads was only 1.1 mm which was too small for castellated holes for any low cost PCB manufacturer. Another issue is that since the SD card connector is at the edge of the PCB, the new interposer PCB would have needed to stick out a little to make room for the castellated holes.

The remaining option was to put SMD pads under the interposer PCB. With 4-layer PCB it would be possible to mount the new SD card connector directly over the old one and the level shifter could be next to the SD card connector. The drawback of this approach is that since the pads are under the PCB it's not possible to solder them with soldering iron and it would require using solder paste and hot air tool.

I did find some discussion if this was possible but I didn't find any actual results, which motivated me to write this post.

Interposer PCB bottom (left) and top (right).

Above is the PCB I designed. It's a 4 layer PCB with mirrored SD card footprint on the bottom that matches the footprint of the incorrectly wired SD card connector. On the other side is bidirectional 1.8 V to 3.3 V level shifter (TXS02612) and 1.8 V regulator. SD card connector footprints are directly on top of each other to minimize the PCB area.

Manufacturing, assembly, and shipping of 5 copies this PCB cost 43 USD.

Soldering

Solder paste manually applied to the SD card connector pads.

I started with applying some solder paste to the pads on the bigger PCB.

Wires for positioning.

I found it hard to position the interposer PCB correctly because the pads are completely covered by the interposer PCB. Since the SD card footprints were exactly at the same location, the two holes in the footprint also overlapped and could be used to position the interposer PCB. I cut some solid core wire and put them in the holes.

Interposer PCB placed with the guide wires.

Using the solid core wires I was able to position the interposed PCB correctly. This wouldn't have been possible if the SD card connector on the interposer would have been soldered beforehand.

I then heated the interposer with hot air to solder it. It was hard to see when the solder paste had melted since the pads were completely covered by the interposer, but I could see some flux bubbling from under the interposer and the solder joints melting on top of the interposer PCB and I determined it was hot enough. I had placed damp paper towel under the bigger PCB to avoid desoldering components on it which worked fine.

Solder joints seen with a microscope.

Solder joints seem fine when viewed with microscope. Although my microscope's image quality isn't too high, there is no visible short circuits and the contacts seems good.

Interposer soldered.

I then soldered the SD card connector on the interposer PCB. It was easy to solder because of the large pads and could be done easily with a soldering iron.

With the added interposer PCB the SD card started to work.

Super glue added.

I added some super glue to the sides for mechanical stability. I didn't think only the solder joints could handle the mechanical stress of inserting and removing the SD card.

Two fixed PCBs.

I also did the same procedure to another PCB which also worked fine.

Conclusion

Fixing incorrectly wired component can be fixed with interposer PCB if there is enough extra space for the PCB to fit into. Soldering it can be difficult and requires hot air tool. Fixing this PCB with the interposer cost about 50 EUR compared to over 500 EUR for respin of the board.

Homemade 6 GHz pulse compression radar

2024-04-03T00:00:00+03:00

Introduction

FMCW and pulse radar architectures.

I have previously made several FMCW radars that have worked well. FMCW (Frequency Modulated Continuous Wave) radar is quite easy and cheap to make. It uses separate transmit and receive antennas, which avoids the need for switching between receiving and transmitting. It mixes the received signal with the transmitted signal, resulting in a low output frequency, making it possible to use low-speed analog-to-digital converter (ADC). However, big, serious radars typically aren't FMCW radars, instead they are pulse radars. Switching one antenna between transmit and receive modes allows them to use just one antenna. When an antenna diameter is measured in meters it matters a lot how many are needed. Pulse radar can use large transmit power without worrying about saturating the receiver, which is a big issue with FMCW radar. Pulse radar is also better for measuring velocity of fast-moving targets as it can transmit pulses more frequently, resulting in larger maximum unambiguous Doppler shift it can measure.

For these reasons, FMCW radars are usually used in short range applications such as automotive radars and aircraft altimeters, while pulse radars are used mainly for long-range applications such as weather radars, aircraft detection, and synthetic aperture radar imaging from aircraft or satellite.

Pulse radar is much more difficult to design than FMCW radar. To share one antenna, very fast switching between transmit and receive is needed. Radar pulses travel at the speed of light, and for example, if switching from transmit to receive takes 1 microsecond, all the reflections from targets in 150-meter distance would be missed during the switching time. Sharing one antenna causes the radar to have a minimum detection distance, which can be hundreds of meters which makes it unsuitable for short-range operation.

Another difficulty is that pulse radar requires much faster ADC to capture the received pulses. FMCW radar mixes transmitted and received waveforms which results in a low-frequency sine wave for each target at the mixer output, for short-range operation, it's possible to use ADC sampling frequency of 1 MHz or even less while using hundreds of MHz of RF bandwidth. Pulse radar requires much faster ADC, typically fast enough to sample the whole RF bandwidth of the transmitted pulse. The range resolution of the radar is determined by the RF bandwidth, and for useful range resolution ADC sampling rate should be hundreds of MHz or even over 1 GHz. This fast ADCs are very expensive and require expensive digital electronics to handle all the data.

This article is about my experiences building a modern pulse radar utilizing fast digital signal processing cheaply.

Pulse compression radar

There are many kinds of pulse radars, and the one I want to make is a pulse compression radar that supports arbitrary waveforms. Generating only linear frequency sweeps could be simpler and sufficient for many practical applications, but it wouldn't be as interesting.

The requirement for arbitrary waveform means that there needs to be a digital-to-analog converter (DAC) with large enough sampling rate to generate the transmitted waveform. The receiver also needs an ADC with large enough sample rate to sample the whole RF bandwidth.

Radar RF side block diagram.

Above is the block diagram of the radar. The architecture is very similar to software-defined radio (SDR) and it could be used as a radio too. The radar has two time-multiplexed receiver antennas with transmitter being shared with one of them. I added the second receiver channel mainly because it was very cheap, it only requires additional switch, LNA and SMA connector. The second receiver channel makes it possible to use the radar also in FMCW mode.

In a proper radar system some filtering would be useful at both transmitter and receiver, but I left it out here to save money.

Superheterodyne and zero-IF (direct conversion) transmitters. Superheterodyne mixing to IF frequency is done digitally.

TX and RX are zero-IF architecture. This is not ideal from a performance point of view but it's the cheapest option. The output of all mixers contains not only the desired frequency-shifted signal but also local oscillator (LO) leakage and image signals, which is the same signal as the desired one but mixed at the opposite side of the LO frequency. If DAC generated the signal at offset frequency it would be possible to filter out the unwanted frequencies at the mixer output with a bandpass filter, but with zero-IF transmitter these unwanted frequencies overlap the signal, making it impossible to filter them out with a fixed filter.

Similarly, these same nonidealities are also present at the receiver. These nonidealities cause distortion of the received waveform, leading to increased range sidelobes for each target.

While superheterodyne architecture would provide better performance, implementing it would require more hardware and my goal is to make a working system with minimal budget. With zero-IF architecture many of the nonidealities can be compensated sufficiently digitally. Predistorting the DAC output signal can compensate for the mixer nonidealities, resulting in a clean output signal. Receiver output signal can also similarly be modified digitally to remove many of the nonidealities if they can be characterized to sufficient precision.

Complex linear frequency sweep signal in time domain and instantenous frequency.

The DAC outputs a complex IQ signal that is modulated by the IQ mixer to the LO frequency and transmitted by the antenna, transmit/receive switch is then switched to receive and reflected signal is sampled by the receiver. Each target reflects some of the transmitted signal and the reflected signal is a sum of the signals from each target.

Complex IQ format allows representing both positive and negative frequencies at the baseband. At the transmitter IQ modulator the I and Q signals are mixed against LO and 90 degree phase shifted LO and summed. The result is that positive baseband frequencies are shifted above the LO frequency and negative frequencies at baseband below the LO frequency.

Pulse compression of the received signal. By correlating with the reference signal the power from pulse is concentrated.

To get the target locations convolution is calculated against the transmitted signal. At the time instance where there was a target the received and transmitted signals correlate and convolution results is large, when there isn't a signal there isn't a correlation and convolution result is small. In practice the convolution is calculated using fast Fourier transform (FFT) as that is faster in practice than calculating the convolution in time domain.

In the above plot sidelobes can be seen around the two targets in the result. These result from the convolution output not being completely zero when the waveform isn't aligned. Multiplying the reference pulse by a windowing function can be used to control the sidelobes of the convolution output. Windowing function can also be applied to the transmitted pulse to further decrease the sidelobes. Drawback of windowing is that it widens the mainlobe and results in slightly worse range resolution. How much sidelobes are traded for resolution can be controlled by the used windowing function.

Range-Doppler processing. Only the amplitude of the pulse is plotted in graph. Phase of the signal is important for Doppler FFT.

Besides the distance to the target, radar can also measure velocity of the target from how phase of the received signal changes during many measurements. By sending a burst of pulses and calculating FFT over the number of pulses dimension, the targets are separated both in velocity and range in the resulting range-Doppler map.

Velocity could be also measured from change of distance, but the beauty of using phase shift of the received signal is that velocity can be obtained from the same measurement as the distance, multiple objects at the same range but with different velocities can be separated, and the measurement accuracy is much better. Detecting multiple objects at the same range with different velocity is important for separating moving objects from stationary objects such as ground, trees, and buildings that can have a large reflected signal that would otherwise mask a small moving object.

Measuring angle of the target would also be possible with multiple antennas, but in this case with one antenna there isn't angle information.

ADC and DAC

2 channel LVDS interface ADCs with >10 bits, sample rate vs price from Digikey.

ADC sample rate is one of the most important parameters for the system as it determines the maximum RF bandwidth that the system can receive. ADC sample rate should be as fast as is affordable. In general, it's much easier to make the RF side and DAC to have greater bandwidth than ADC, and it's ADC bandwidth that limits the system.

The requirement for ADC is having at least two channels, this is required for IQ sampling, and LVDS output interface. Two one-channel ADCs could also be used but it's disadvantageous from PCB area and routing perspective. The fastest ADCs usually have JESD204B digital interface, the problem with it that it requires high-end FPGA with high-speed serial transceivers and those are in general too expensive for my budget. LVDS is the highest speed interface that can be connected to regular FPGA I/O pins.

In the above plot are all 2 channel ADC with LVDS interface and at least 10 bits. The best sample rate for price is ADS4229 with 250 MHz sample rate for 58 EUR / piece in single quantity. Even higher ADC sample rate would be very desirable, but any higher sample rate than this would get much more expensive. There is one two channel 8-bit ADC with 500 MHz sample rate for 73 EUR / piece, but it has 20 dB lower SNR than the 12-bit ADC and doubling the sample rate would only give back 3 dB SNR. Low bit ADC would decrease the dynamic range of the receiver making it more prone to saturation, and it would require more gain before the ADC, so I decided against using it despite the higher sample rate.

Suitable DACs are easier to find, and I chose to use DAC3174 two-channel 14-bit 500 MHz DAC costing 33 EUR / piece. While the system bandwidth is limited by the ADC, it's useful to have more than enough bandwidth on the DAC to make filtering easier.

ADC filter

ADC requires anti-aliasing filter before it to limit the signal frequency to below half of sample rate (Nyquist rate) to avoid aliasing. To get the largest usable bandwidth the cutoff frequency of the anti-aliasing low-pass filters should be as close as possible to the Nyquist rate, but this makes implementation of the filter difficult as it needs to have very sharp cutoff.

Filter should also have equal amplitude and group delay on the passband. Amplitude requirement is easy to understand, we don't want to have different frequencies attenuated different amounts. Group delay measures how much different frequencies are delayed by the filter. If the group delay difference is too large for different frequencies, the received pulse is distorted by the filter decreasing its correlation to the reference pulse. In practice, this shows up as higher sidelobes.

ADC lowpass simulation setup.

Source impedance of the IQ demodulator is 50 ohms differential. ADC input is also differential, and its impedance varies with frequency having high impedance at lower frequencies, but at higher frequencies the input capacitance is significant. ADC datasheet provides a model for the ADC input which I added to the simulation setup. It suggests adding a resistor at the input that sets the input impedance, series resistors to limit ringing due to bond wires and additional resistor and capacitor across inputs to filter sampling glitches. While adding a 50 ohm resistor across the ADC input would be good for filter design perspective it attenuates the signal too much as there already isn't enough gain in the receiver and the IQ demodulator linearity decreases with low output impedance. I added instead 200 ohm resistor to minimize the signal attenuation. This makes the filter design challenging, as the high load impedance requires using small capacitors and large inductors. Higher impedance also increases the effect of sampling glitches, which are caused by ADC input sampling capacitors rapidly sampling the input signal. Adding IF amplifier would have made the filter design easier.

100 nF series capacitors decouple the DC levels of IQ demodulator and ADC. While it would be good to have DC coupled signals, the DC levels of IQ demodulator and ADC are different and any significantly different DC levels would limit the maximum AC signal range.

Simulated frequency response of the ADC lowpass filter. Nyquist frequency marked with vertical line.

The cutoff frequency of the filter is set at 100 MHz and there should be -20 dB attenuation at the Nyquist frequency of 125 MHz. Up to about 60 MHz both magnitude and group delay are very good, above that it could be better but its hard to improve with these constraints. There is some variation in the passband magnitude that would have been smaller with 50 ohm impedance. Group delay is relatively good at medium frequencies, at very low frequencies AC coupling capacitor causes the delay to shoot up and near the cutoff frequency there is a peak in the delay. The filter response can be compensated digitally if its a problem.

DAC anti-alias filter

Simulated frequency response of the DAC lowpass filter. Nyquist frequency marked with vertical line.

Digital-to-analog converter is also a sampled system, and it has unwanted aliases at the output that need to be filtered out. The sample rate of DAC is 500 MHz which compared to required signal bandwidth of 100 MHz makes the filter design much easier. The alias frequencies are in the range 400 to 500 MHz for 0 to 100 MHz signal.

The filter is designed to have flat magnitude and group delay below 100 MHz and in the simulator both look very good. Cutoff frequency is just above 100 MHz so that the peak in group delay is above 100 MHz. The aliases are much further away in frequency than with the ADC, and they are attenuated at least 65 dB more than the signal. This amount of attenuation is more than enough for the DAC aliases to not cause any issues, but it does mean that they are visible at the RF output. If the signal power is 30 dBm, then the image signal is about -35 dBm. For proper radar the attenuation likely should be higher to avoid radiating power at other than the allocated frequency band.

FPGA

Xilinx Zynq FPGA block diagram. The chip has two-core ARM CPU and programmable logic with fast interconnect between them.

Using just a microcontroller isn't possible for this application. FPGA is required for accurate timing of pulse generation and for managing the ADC and DAC data. Accurate timing of pulse generation is critical for proper operation. Switching between transmit and receive needs to be done quickly and accurately, any timing error in pulse triggering or in the receiver will be visible as large distance error.

Pricing of the FPGAs is very bizarre. Looking at Digikey or other resellers many of the suitable parts have prices starting in hundreds of dollars and better ones can cost several thousand. However, the exact same parts can be found for fraction of price from China. For some reason, Zynq 7020 is one of the cheapest Zynq FPGAs in China available at $17, while the exact same part from Digikey costs $173.

Zynq 7020 has dual-core ARM-A9 CPU and typical FPGA programmable logic in the same package. Having also a CPU core is useful as it can handle communication to PC. It can also run Linux and I added SD-card for Linux file system if I want to use it, but initially software is running without any operating system.

Digital design

Block diagram of digital interfaces.

With fast ADC and DAC moving a lot of data, it's important to consider whether the system can keep up. In the above block diagram, digital interfaces between important blocks have been drawn. The FPGA SoC consists of two parts: processing system (PS), which is dual-core ARM A9 CPU, and programmable logic (PL), which is programmable FPGA fabric. They are connected to each other through with four 64-bit AXI buses. Their clock frequency is configurable and, in this case, it's set to 130 MHz which is near the upper limit that it can work. One AXI bus is reserved for ADC Direct Memory Access (DMA) and other for DAC DMA, there's also a third, lower speed AXI bus (not drawn in the diagram) for configuring the registers in the programmable logic.

A fast connection to the PC is needed to quickly transfer captured ADC samples. Initially, the digital processing will be done on PC, but it should be possible to do it on FPGA too for some applications. If the interface to PC is much slower than the ADC data generation rate, it limits how often the radar can be triggered. For target tracking, this means slower update rate of target positions.

1 Gbps Ethernet is the fastest interface to PC that can be easily connected to this FPGA chip. USB 3 is another possible choice, offering 5 Gbps speed with easy connection to PC, but it would require an external USB 3 transceiver chip and more effort to make it work.

The system has a single DDR3 DRAM chip that is connected to the PS side of the FPGA. While the memory chip could be clocked faster, the memory interface speed is limited by the FPGA memory controller to 1066 MHz. Memory bus width is 16-bits. The memory controller supports up to 32-bits, but it would require adding a second DDR3 chip and the higher bandwidth is not necessary in this system.

ADC samples are received by the PL side, which has a small FIFO buffer and DMA controller transfer them to DRAM through the PL side. DAC also has its own DMA channel, but DMA uses only one AXI bus limiting it to 8.3 Gbps, which is less than what the DAC needs. It's also important to note that DDR3 bandwidth is less than the sum of the DAC and ADC bandwidths, making streaming DAC samples from DRAM while storing ADC samples at the same time impossible. For this reason, there is a small 1 MB memory on the PL side that stores DAC samples. Pulse samples are transferred from PC to DRAM through Ethernet, then DMA transfers them to the small memory on the PL where they are transferred to the DAC every pulse.

A small DAC memory limits the pulse length to 130 µs, but it's plenty for pulse radar. A 130 µs pulse corresponds to 20 km minimum detection distance, and typical pulse length is about 1 µs. The pulse could also be generated on PL, eliminating the need for memory, but lookup table implementation makes it easier to change pulse parameters such as windowing function, pre-distortion, and test different types of pulse waveforms.

RF design

RF parts take only a small portion of the PCB area. It's also a small amount of required work on the project although it seems like it should be the important part.

With the digital parts out of the way it's time to look at the RF side. Designing the RF parts is relatively straight forward. Similar to my previous radars, the operating frequency will be around 6 GHz. This is the highest frequency with many off-the-shelf cheap components due to many consumer applications.

RF part consists of: IQ modulator, IQ demodulator, PLL for generating the LO frequency, power amplifier, low noise amplifiers and switches.

IQ modulator should have low LO leakage, high image rejection, enough output power to drive PA without needing another amplifier, and baseband voltage level compatible with the DAC output voltage range. There aren't that many possible commercial chip alternatives and most of them are very similar in performance. Same applies also to the IQ demodulator.

Choosing a power amplifier was more difficult. While big, expensive radars often have transmit power measured in kW or even MW, but that's unrealistic in this case. I would like to have at least 1 W peak RF power but there are surprisingly few choices at 6 GHz band despite WLAN applications that require power amplifiers. The best suitable amplifier I found was Skyworks SE5004L, which has 2 W typical output 1 dB compression point and high gain of 32 dB, but its documentation is severely lacking. There isn't any graph of gain vs frequency and it requires some external components, but there aren't any values for them in the datasheet. The solution for external components is found in the SE5004L-EK1 evaluation kit documentation, which has the schematic of the evaluation board of this chip. It's also out of stock at the moment at common resellers although it's available at some Chinese resellers. In the end I did decide to go with it because there aren't many other cheap alternatives with enough output power.

Switching speed of the T/R switch is very important, and it should have high enough power handling capability to handle the 1 W power amplifier output without blowing up or distorting the signal. Especially the fast switching speed is a though requirement that rules out many options. I ended up choosing MASW-007588 switch that has 55 ns switching speed and 37 dBm 1 dB compression point. While 55 nanoseconds is fast, in that time light travels 16.5 meters. There are better switches specifically made for this kind of applications, but they are too expensive for my budget.

Another option would be to use circulator instead of switch. This is common for higher power radars as circulators can handle hundreds of Watts of power, and there is no switching speed. There are some circulators for this frequency, but big issue with them is that they are very large and much more expensive than simple switch.

The receiver should have enough amplification that the RF noise floor is above the ADC quantization noise floor. The RF noise floor spectrum at the ADC input can be calculated as $kT$, where $k$ is the Boltzmann constant and $T$ is temperature in Kelvin. This results in power density of about -174 dBm/Hz at room temperature.

LNA amplifies the thermal noise and adds some noise to it which is determined by LNA's noise figure. Switches and PCB lines have some losses. IQ demodulator's voltage conversion gain can be used to calculate the output voltage density at the ADC input.

ADC noise floor can be calculated from SNR specification, 69.4 dBFs (decibels relative to full scale) in this case, sample rate 250 MHz, and maximum input voltage 2 V peak-to-peak (0.707 Vrms). Noise is then 69.4 dB below 0.707 Vrms maximum input voltage for each sample, and there are 250 million samples in one second which equals bandwidth of one Hertz. This gives the ADC noise floor density of -156 dBV/Hz.

Calculating the RF noise floor at the ADC input after considering the whole signal chain from starting from LNA gives noise floor of about -155 dBV/Hz. This is barely not enough gain. RF noise floor should be much higher than the ADC noise floor, typically about 10 dB, so that the ADC quantization noise doesn't increase the noise of the whole receiver. An ADC driver amplifier could easily have enough gain, but low-frequency amplifiers with high enough bandwidth are surprisingly expensive. In the end, I just decided to have few dB higher noise floor.

Maximum detection range

The maximum detection range of the radar can be calculated as following:

The transmitter transmits a pulse of length $t_s$ with average power of $P_t$, which is radiated by the transmitter antenna with gain $G$. The power density ($W/m^2$) at distance $r$ can be written using Friis' equation as $P_t G / (4 \pi r^2)$. This power is reflected by a target with a radar cross-section of $\sigma$ and some of it is reflected back to the radar. The received power depends on the effective area of the receiving antenna: $P_r = P_t G A_e / ((4\pi r^2)^2)$. $A_e$ can be written in terms of the antenna gain as $A_e = \lambda^2 G / 4 \pi$, where $\lambda$ is the wavelength of the RF signal. The equation for the received power at the receiver input can be written as:

$$P_r = \frac{P_t G^2 \lambda^2 \sigma}{(4\pi)^3 r^4}$$

This is the received power from one pulse. To increase the received power, multiple received pulses can be coherently summed. It's important that the summation is coherent so that the phases of the received pulses are aligned. In practice, instead of summing, an FFT is used so that power from moving targets can be coherently summed and separated from each other.

To get the maximum detection range, we need to find the minimum detectable received power. The detection performance is limited by the noise of the receiver. Thermal noise density (W/Hz) of the receiver is $kT$, where $k$ is the Boltzmann constant and $T$ is the receiver temperature in Kelvin. The receiver amplifies this thermal noise and adds its own noise to it. The noise factor, $F$, of the receiver is how much higher the noise floor of the output is compared to theoretical thermal noise floor if there wouldn't be any added noise. This can be calculated from the receiver gain, RF amplifier's noise figure and ADC's noise floor.

To get the noise floor, we need to multiply the thermal noise density $kT$ by the receiver noise factor $F$ and the receiver's noise bandwidth $B$. The correct noise bandwidth to use is the minimum bandwidth after all the signal processing which noise can't be separated from the signal. For example, by taking the Fourier transform of the input signal, we can discard all the frequency bins that are beyond where our signal is, and noise at those discarded frequencies won't affect the detection capabilities of the receiver. Pulse compression ideally collects all of the power of a pulse within a bandwidth of $1/t_s$ for a linear frequency sweep. However, in practice, FFT windowing functions and any mismatch between reference and received pulses will decrease this slightly.

The minimum detectable signal should be higher than the noise floor by some margin. The threshold value for detections can be chosen freely, but there is a trade-off: if we accept detections that are only just above the noise floor, occasionally some of them may be false detections resulting from noise just happening to be above the detection threshold. The probability of false alarm depends on the method used to estimate the signal-to-noise ratio of the detection. For an ideal detector, the false alarm probability can be calculated based on the probability that normally distributed noise is above the detection threshold. Common threshold value is usually around 13 to 15 dB.

At the maximum detection distance the received power is equal to minimum detectable signal:

$$\frac{n P_t G^2 \lambda^2 \sigma}{(4\pi)^3 r^4} = \frac{kTFS}{t_s}$$

,where $n$ is the number of pulses, and $S$ is the detection threshold compared to the noise floor. Solving for $r$ gives the maximum detection range:

$$r_{\text{max}} = \sqrt[4]{\frac{n t_s P_t G^2 \lambda^2 \sigma}{(4\pi)^3 kTFS}}$$

Variable	Explanation	Value
$P_t$	Transmitted power	30 dBm
$G$	Gain of antennas	14 dBi
$\lambda$	Wavelength	5.2 cm
$\sigma$	Target radar cross-section	1 m²
$T$	Receiver temperature	290 K
$t_s$	Pulse length	1 µs
$n$	Number of pulses in burst	1024
$F$	Receiver noise figure	5 dB
$S$	Detection threshold	15 dB

In the above table are estimations of the radar system parameters. Plugging these values in the equation gives a maximum detection distance for target with 1 $m^2$ radar cross-section of 1200 meters. This might be slightly optimistic, as there are losses in the cables to antennas, loss from antenna efficiency, losses from mismatch, and atmosphere attenuation. However, the maximum detection distance should still be about 1 km. At this maximum distance the average received power from a target is equal to the minimum detection threshold. Therefore, on average, a target at this distance is detected 50% of the time. Due to normally distributed noise, there is a chance that a target at shorter distance is not detected, and a target at longer distance could be detected. However, because of the fourth power dependence of the received power, the probability of detection drops quickly at larger distances.

PCB design

Simplified PCB block diagram. PLL generates 6 GHz RF local oscillator and clock generator generates clocks for ADC, DAC and FPGA.

Practical implementation of the system requires designing a printed circuit board (PCB) that integrates all the components. The system has both RF and high-speed digital circuits that require careful PCB routing to make sure that they function correctly.

The PCB has six layers, and I don't think the FPGA can be routed with any less layers. The material is standard FR-4, which isn't ideal for RF routing since it's quite lossy, but it isn't a big issue in this case since the RF trace length is kept very short.

DDR3 routing

DDR3 routing implementation. Source: UG933

DDR3 DRAM memory connected to the PS side of the FPGA runs at 533 MHz clock frequency with two transfer per clock cycle. The memory uses the DDR3L standard, which is a low-voltage version of the DDR3 standard with a 1.35 V operating voltage instead of the normal DDR3 1.5 V supply voltage. While this isn't very fast by the modern standards, it still requires some care with the routing. Memory traces should be length matched, have correct characteristic impedance, and be terminated properly to minimize reflections.

The nominal characteristic impedance of DDR3 traces is 40 ohms. A shared address bus is fly-by routed to all memory chips and terminated with a 40 ohm resistor to VTT supply, which is at half of the memory supply voltage. Each memory chip has its own data traces with on-chip termination. There are also few control lines that are routed to all memory chips. With only one memory chip on the PCB, the routing is much simpler.

The memory bus can be simulated with circuit simulators before being manufactured. Professional programs have ways to do finite element simulation of the PCB, but this is quite difficult with open source software. FPGA and memory chip driver and receiver electrical models are provided as IBIS files. I used KiCad to design the PCB and it's supposed to include IBIS support but it was unclear how to use it. I ended up using SPISim_IBIS web app to convert the IBIS models to SPICE netlists and simulate them with ngspice.

DDR3 memory routing simulation of a single trace.

I was interested in simulating if address bus termination resistors can be left out in this case where there is only one memory chip, and it's mounted close to the FPGA. I have seen this done on at least one FPGA development board, and it would save some PCB space if termination resistors could be left out.

DDR3 databus with 40 ohm line and termination.

Normally, an eye diagram is used to analyze the timing margin of the memory bus. However, it's not easy to simulate it with ngspice, so I just added a pulse source and did a transient simulation plotting the voltage at the memory chip input. With 120 ps line delay, 40 ohm line impedance, and termination resistance the memory chip input voltage looks fine. High and low thresholds are 0.81 and 0.54 V according to the memory chip datasheet, and the signal looks very good in the simulator.

DDR3 databus without termination resistors.

Without termination resistors, the voltage looks fine from the threshold level point of view. However, there is significant under and overshoot. Supply voltages are 0 V and 1.35 V, and the memory chip input voltage overshoots by about 0.7 V, which is enough to forward bias the ESD (Electrostatic discharge) protection diodes of the memory chip. This might be fine in practice, but memory chip datasheet says that the overshoot should be limited to maximum of 0.4 V. For this reason, I added the address line termination resistors.

DDR3 databus with 60 ohm line and 50 ohm termination resistors.

While removing the termination resistors violates the datasheet guarantees, it's possible in this case to use 60 ohm line impedance and 50 ohm termination resistors with minimal difference in the signal integrity. The benefit of using higher line impedance is that it results in narrower line on PCB allowing for denser layout. A 40 ohm trace is 0.24 mm wide, while 60 ohm trace is 0.10 mm wide. Using narrower trace also allows having more distance between different traces, which decreases cross-talk between traces. 50 ohm termination resistor is close enough to the trace impedance, and since 50 ohms resistors are needed on other places on the PCB, using 50 ohm resistor allows removing one resistor value from the bill of materials, making the assembly slightly cheaper.

DDR3 routing. FPGA on the right and DDR3 chip and the termination resistors on the left. Top left is the top layer and bottom right is the bottom one advancing horizontally.

Above is the final DDR3 routing on all the PCB layers. Layers 2 and 5 are ground, 4 is supply voltage, and others are reserved for signals. Two grounds are needed for correct impedances on the top, middle, and bottom traces of the PCB. With only one ground plane, the distance from the signal to ground would be too large on either the top or bottom layer. Data bus traces are swapped within the byte boundary to make the routing easier. The traces are length-matched with squiggly lines, and some traces are manually drawn on the ground and supply layers to decrease the size of slots in the planes due to vias. The trace matching requirement is ±10 ps according to the Zynq PCB design guide, which is approximately ±2mm in trace length. However, considering the faster memory chip and having only one memory chip, the actual margin should be much greater. There is also some delay difference inside the FPGA package which should be considered in the length matching.

Transmission line termination

The T/R switch needs to be switched as fast as possible to minimize dead time between transmit and receive, and the same applies for the IQ modulator enable pin. The FPGA I/O pin driver strength can be controlled, and with the highest drive strength it has a rise time of about 400 ps at the switch input in simulator. However, few centimeters of PCB trace between the FPGA and switch input functions as a transmission line, which has significant effect at these frequencies.

The switch input pin is not matched to 50 ohms, and a typical CMOS input has high input impedance. This causes reflections, which severely distorts the switching waveform.

Termination of switch input with capacitor and resistor.

To minimize reflections, the transmission line should be terminated to the characteristic impedance of the transmission line, which is 50 ohms in this case. Placing a 50 ohm resistor to ground near the switch input pin would work, but it would sink DC current and cause the DC voltage to drop. Termination to supply voltage has a similar issue except that now voltage can't reach 0 V.

Termination with a 50 ohm resistor in series with a small capacitor solves the DC level issue. Capacitor value should be tuned so that high-frequency reflections are absorbed without affecting the low frequencies too much.

Simulation of switch voltage with and without termination.

Above is the simulated voltage at the switch input. Transmission line length was 300 ps, and termination capacitor was set to 12 pF. Without termination there is significant over and undershoot, and a risk that the voltage drops below the threshold voltage slowing the switching. With the termination, the waveform is much cleaner.

Power supply

Analog electronic components are sensitive to supply voltage noise. This is especially important for RF receiver with input signal at the level of the thermal noise floor.

Switching regulators have good efficiency, often around 90%, but their output has switching noise that is significantly higher than the thermal noise floor. If this noise isn't filtered properly, it will couple into the received and transmitted waveforms and cause interference at the receiver. A linear regulator, often called low-dropout regulator (LDO) for historical reasons, functions as a variable resistor, dissipating enough power to ensure that the output voltage is at the correct level. The output noise is much lower, but if the voltage drop is too large the efficiency is terrible.

Power supply rejection rate (PSRR) of TPS7A7001 LDO.

To have both good efficiency and low noise, it's common to have a switching regulator followed by an LDO to filter the switching noise. However, this isn't enough filtering in this case. LDO filters well very low frequencies, but it's filtering capability drops at the higher frequencies. Above is the power supply rejection ratio (PSRR) of the LDO I'm using. For example, with a 1 mV amplitude, 2.5 MHz signal at the LDO input is attenuated by about 15 dB, resulting in about 200 µV amplitude signal at the output.

The requirement for minimum power supply filtering can be obtained with few assumptions about the coupling of the noise. The smallest signal level is at the input of the receiver LNA. The thermal noise floor is -174 dBm/Hz at room temperature. With a 10 ms measurement time, the bandwidth is 100 Hz. This results in a maximum of -154 dBm power at the LNA input. At 50 ohm impedance, this corresponds to 5 nV RMS voltage. If the LNA supply voltage is modulated by noise, it affects the gain of the amplifier, and the supply voltage noise is mixed to the RF signal. In practice, the allowed noise amplitude can be larger since there is usually some power supply rejection at the LNA for low-frequency supply voltage noise to the output RF frequency, but it's usually not specified in the datasheet. With a 10 mV worst-case switching noise amplitude, the required attenuation is 120 dB to reach the noise floor. LDO can be assumed to filter about 10 dB, and we can assume another 10 dB power supply rejection from the RF components, which sets the power supply filtering requirement to 100 dB.

Two-stage ferrite bead filter schematic. Capacitor parasitics drawn individually.

The required power supply filter can be designed with ferrite beads. They are inductors that are lossy at high frequencies. A capacitor is needed after the ferrite bead to complete the low-pass filter. The series resistance and inductance of the capacitor are crucial at these frequencies, and they are included in the schematic, assuming an SMD ceramic capacitor.

Ferrite bead filter frequency response.

The above filter achieves 100 dB attenuation at 1 MHz. The switching frequency is 2.5 MHz, and this filter works well at that frequency. However, it has a resonance at 30 kHz, which increases the noise at the output at that frequency. This is caused by the ferrite bead behaving like an low-loss inductor at low frequencies which resonates with the capacitor due to a lack of resistance that would dampen the resonance. It can be fixed in two ways: adding resistance in series with the capacitor or increasing the capacitance. Resistance could be also added in series with the ferrite bead, but this is possible only if the DC current is small.

Ferrite bead filter frequency response with 20 µF first capacitor and 200 µF second capacitor.

With larger capacitors, the resonance is much smaller, and the attenuation increases slightly.

Time domain response to 1 A current step. One ferrite bead with 200 µF capacitance. The response is underdamped and increasing capacitor ESR would decrease the oscillation.

An important limitation of the ferrite bead filter is its time domain response. If the output current changes quickly, the inductance of the ferrite bead tries to keep the current through it constant, which means that the output capacitor needs to supply the high-frequency current. If the output capacitor is small, it can't supply the current, and the output voltage drops. If there isn't enough resistance either in series with the ferrite bead or in series with the capacitor, the output voltage oscillates before settling. Especially the power amplifier that has high current draw needs a lot of capacitance to ensure that the supply voltage doesn't drop as it's switched on.

The time domain response can be improved by placing the ferrite bead before the LDO. The LDO is then able to keep the output voltage constant while the input voltage dips, but it needs to be ensured that the voltage after the ferrite bead doesn't dip too low so that the LDO stays in regulation. I placed one ferrite bead before the LDO and a second one before each analog component. The first one filters the switching noise, and the second ferrite bead adds additional filtering for each IC. Besides filtering the switching noise, the second ferrite bead for each IC also improves the isolation between components, which is desired between transmitter and receiver. Having a ferrite bead close to each component also reduces the length of the trace that can work as an antenna to pick up radiated noise.

In total, the PCB has nine different supply voltages. There are six supplies for FPGA and digital electronics: 1.0 V for FPGA core supply, 1.8 V, 2.5 V, and 3.3 V for various digital chips, 1.35 V and 0.675 V for DDR3 RAM. The noise on these rails isn't too important for the system performance. Analog electronics have low-noise 1.8 V, 3.3 V, and 5.0 V rails with linear regulators and ferrite bead filtering.

ADC and DAC routing

ADC data trace routing to FPGA. ADC footprint on the right side, FPGA out of view on the left side.

The ADC connects to the FPGA with a 12-bit wide LVDS bus. The ADC also generates a clock signal that is center-aligned to the data. The sampling rate of the ADC is 250 MHz, and there are two channels with one channel's data on the rising edge and the other on the falling edge of the clock. This data rate is too fast for the FPGA to capture statically, requiring dynamic capture that uses adjustable delay lines to correct for the signal delay programmatically. These delay lines also make the length-matching requirement for the PCB routing quite loose.

The DAC also has an LVDS interface but it operates at 500 MHz with 14-bits. This FPGA doesn't have adjustable output delay lines, so the line lengths must be length-matched to make sure that the DAC can capture the data. The DAC datasheet provides setup and hold times for the interface, and plugging these values into the FPGA synthesizer tool indicates that the timing can be met with ±25 ps trace delay, which corresponds to about ±4 mm difference in the data trace lengths compared to the clock trace. Even higher delay might work, but it's good practice to match the interface as well as possible, especially since it can't be adjusted in software like the ADC interface.

On the FPGA side, it's important to set the supply voltages for the banks with LVDS to 2.5 V with this FPGA part. For the receiver, only this voltage works correctly with internal 100 ohm termination. Using internal 100 ohm termination instead of external 100 ohm resistors on each data line makes the routing easier and saves PCB space. The DAC LVDS transmitter also needs a 2.5 V supply voltage for both common mode and differential voltages to be compatible with what the DAC expects.

1 Gbps Ethernet

Ethernet chip schematic connections. The chip requires several configuration resistors.

The Ethernet interface needs an external PHY chip that is between the Ethernet connector and the FPGA. The cheapest one I could find was Realtek RTL8211F, which can be found for $1 in single quantities from China. While the RTL8211E version of the chip is found on many FPGA development boards, the F version is much more uncommon. The challenge with this chip is that officially the datasheet is provided only under NDA. However, it is available from the Chinese resellers with big "Confidential" and "Not for public release" labels. However, the datasheet isn't quite clear on how it should be connected, and there aren't any example schematics in it. Searching this chip on Google, I did find few schematics of boards using it, which gave me some confidence that I can wire it correctly. See the above schematic on how it should be wired for FPGA if you are also looking to use it.

Important note about the Zynq FPGA is that the Ethernet interface doesn't meet the RGMII interface (FPGA to Ethernet chip interface) specifications when used with 3.3 V supply voltage. Because of this, I had to set the FPGA PS side supply voltage to 1.8 V, which requires adding level shifters for SD card and UART that are powered from the same voltage.

JTAG and debug UART

FPGA is programmed and debugged with JTAG connection. On development boards there is usually a connector and external JTAG debugger is used to connect to the development board. The official JTAG debugger is quite expensive with $270 list price and I don't want to pay for one.

FTDI makes FT2232H chip that can convert from USB to JTAG and UART. This can be used to implement the JTAG interface cheaper. There used to be a drawback that it wasn't supported by the Xilinx official tools which made debugging the design much harder, but now it's officially supported if the EEPROM memory is programmed with tool provided by Xilinx.

FT2232H also has UART output that is useful for debugging the ARM processor code. Calling printf in the processor code prints characters to the debug UART.

Clock generator

Simplified block diagram of clock signals.

Accurate timing of the whole system is very important. Several clock signals are unavoidable since the ADC runs on 250 MHz, the DAC runs at 500 MHz, and the FPGA requires even lower clock frequency. The FPGA does have several phase-locked loops that can be used to generate clocks, but accuracy of their output isn't good enough. For a 100 MHz clock the tools predict a peak-to-peak jitter of 130 ps, while the clock generator chip has about 4 ps peak-to-peak jitter. ADC and DAC require very clean clocks with minimal jitter, and any timing error on the sampling clock reduces the signal-to-noise ratio.

Everything involved in the radar signal generation or processing should run on synchronized clock signals. For example, if the ADC and DAC would run with completely unrelated clocks, the pulses wouldn't stay synchronized in phase as the clocks would slightly drift. Phase drift would make coherent summing of multiple pulses impossible and seriously harm the performance of the radar.

There are two unrelated clocks on the PCB. PS side of the FPGA has its own 33 MHz crystal and it generates clocks for DDR3, CPU, and peripherals from it. 133 MHz bus clock is also generated from it, which is passed to the programmable logic side of the FPGA. The PL side uses an external clock generator chip CDCM6208 to generate several 250 MHz and 500 MHz clocks from a single 25 MHz crystal. These clocks are all phase synchronized to each other. The PS side's own independent clock is that on power up the clock generator has not been programmed yet. The PS side has its own independent clock, which is needed for programming the clock generator. The independent clock domains of PS and PL don't cause issues with proper clock domain crossings.

The ADC outputs a 250 MHz clock with the data to the FPGA, which is internally divided by two and used to clock the pulse timing logic. This makes the FPGA logic also synchronized to the clock generator. Frequency division is required because 250 MHz clock is too fast for the FPGA logic. The clock division makes that for each 125 MHz clock cycle, two ADC samples are received from both channels for total of 48 bits of data. There is a FIFO for clock domain crossing to the PS side's 133 MHz, and DMA transfers the samples through a 64-bit AXI bus to the DDR3 memory. 133 MHz is used because it needs to be faster than the 125 MHz input clock and this clock needs to be generated by PS so it can't be the PL 125 MHz clock.

The FPGA needs to output a 500 MHz clock with the data to the DAC, and for this purpose, a 500 MHz signal is routed to the FPGA. The FPGA has internal clock generators, but they are not used for this purpose because their jitter is too high. 500 MHz is too high frequency to route on the global clock network of the FPGA, but it's possible to route it on the I/O clock network that is only routed to the I/O buffers. That means no logic can be clocked at 500 MHz, but the chip has serdes that can be clocked from the I/O clock at each pin, which can take four bits at the rising edge of the 250 MHz clock and output them at both rising and falling edges of the 500 MHz I/O clock.

Manufacturing

Half populated PCB received from the PCB manufactuer.

I ordered the PCB from a Chinese manufacturer, including assembly. They sent me two assembled pieces and three empty PCBs. Some uncommon components were not available for assembly, and I had to order those separately and solder them myself. These included all the most expensive components such as ADC, DAC and PLL. Luckily, the FPGA was available for assembly, which saved me the trouble of soldering the large 484-pin BGA package myself.

Quality of the PCB looks good, especially considering the price, which is only a fraction of what it would have costed me locally. However, only one of the two assembled PCBs worked out of the box because of soldering issue with one of them.

The suspiciously cheap $15 FPGA had equally suspiciously date and lot codes covered (white rectangles on the FPGA chip in the picture above). I have a development board of the same series chip with markings intact, so it definitely shouldn't look like this. It did end up working, but I wonder what the origin of these chips is.

Fully populated PCB.

I soldered the rest of the components myself using solder paste and hot air tool. It would be difficult to solder the QFN packages without hot air tool on already populated board.

Backside of the PCB.

Two-sided assembly would have costed extra, so all the components are placed only on the top side. There are some places for additional decoupling capacitors on the bottom side just in case, but those were not needed.

JTAG programmer

Vivado hardware manager. ARM processor, Zynq 7020 FPGA connected to FTDI chip connected to localhost.

The first step to bring up the board is to program the FT2232H chip, which functions as JTAG programmer and serial port. Xilinx has program_ftdi tool that can program its EEPROM so that Xilinx tools recognize it. I first had problems with the tool not recognizing the device. It failed to find the ftdi device, even though I could see it in the Linux system log. After installing some ftdi libraries and making sure that the official ftdi tools were able to read the EEPROM, I was able to successfully program the EEPROM with the program_ftdi tool.

Checking the Xilinx Vivado hardware manager, it's now able to find the Zynq 7020 FPGA. Programming and debugging the FPGA now works with the Xilinx tools.

FPGA programming

FPGA programmable logic block diagram.

FPGA software consists of ADC and DAC LVDS interfaces, pulse timing that enables and disables switches, PA, LNAs and other components at the right time, AXI registers that enable the PS to configure the programmable logic, two DMA channels for ADC and DAC samples, and SPI interfaces for ADC, DAC, PLL, and clock generator.

Most of the signal processing is done on the PC, and the FPGA mainly passes the data around. However, it would be a good idea to have digital filtering and decimation for the received samples on the FPGA. When the transmitted pulse bandwidth isn't very large, for example when it isn't centered at zero frequency, it's possible to do mixing digitally, filter the samples, and reduce the sample rate. This would enable reducing the amount of data that needs to be sent to PC and increase the frame rate of the radar.

LVDS receiver. Source: xapp1017

LVDS receiver is based on Xilinx appnote xapp1017. It connects two delay lines and flip-flops to each LVDS lane with delay difference set so that they sample the signal with 1/2 bit delay. State machine changes the delays so that the master flip-flop samples at the center of the data eye. The dynamically adjusted delay is able to compensate for PCB routing and FPGA internal delay differences.

Part of the radar pulse timing circuit VHDL code.

The pulse timing circuit is just a counter with equality comparisons for each possible event that can be programmed with AXI registers. The timing circuit is triggered from the PS side of the FPGA, starting the counter that triggers every subsystem on the FPGA and every external chip at the exact correct clock cycle. It also has a loop functionality that can trigger the pulse multiple times with precise repetition interval to support sending a burst of pulses.

Accurate timing of the burst is essential for accurate target velocity measurement. Any timing inaccuracy between ADC and DAC transfers to inaccuracy in the measured distance. A single 125 MHz clock cycle timing error in ADC or DAC triggering translates to a 1.2 m error in the measured distance.

Receiver noise

Testing the radar without antennas.

For bench top testing I put matched loads at the antenna connectors, disabled transmitter and recorded the ADC output. Ideally the recorded signal would be noise and any signals visible are unwanted interference.

ADC output spectrum without signal, 5.80 GHz LO.

The length of the recording is 33 ms which is 8 million samples. The noise floor average is -139 dBFs which is about what it should be. However, there are several interference signals visible, the biggest are multiples of 25 MHz. Their amplitude is about -100 dBFs which corresponds to about 15 µV RMS at ADC input, so they aren't very large. DC offset of the ADC is also visible as very large peak at zero frequency.

The source of the interferences is fractional spurs caused by the PLL. They can be changed by changing the PLL output frequency, PLL settings and LO input reference frequency.

ADC output spectrum without signal, 5.75 GHz LO.

The spurs are minimized when PLL output frequency is integer multiple of the PLL reference clock. PLL reference clock is 250 MHz, but this is too high speed to run the PLL phase detector, and it is divided by two by the PLL reference input divider. With 125 MHz PLL reference clock setting the output frequency to 5.75 GHz makes it integer multiple and almost completely gets rid of the spurs. 5.875 is another close multiple that works well also with RF electronic side. There is still a spur at -125 MHz, but this is expected as it is the phase detector frequency.

ADC output spectrum low frequencies.

Noise floor of the ADC is higher at low frequencies due to 1/f noise of the ADC. Switching frequency of the DC/DC converters is 2.5 MHz and it's not visible at the output spectrum plot, which means that the supply filtering works as designed.

Transmit power

The power amplifier I'm using has an integrated power detector. I set the DAC output voltage to 85% of maximum amplitude, which is about the maximum amplitude it can go while leaving some room for DC offset for LO leakage cancellation digital predistortion. This should result in around +3 dBm output power from the IQ modulator, and with 32 dB power amplifier gain it should be enough to drive the PA into compression.

PA power detector voltage measured on oscilloscope.

The power detector pin waveform looks correct when measured on oscilloscope. It has a series of 2 µs long pulses, which was the pulse width. Peak voltage is 1.72 V and about 0.32 V when not transmitting.

Power detector pin voltage vs output power from the datasheet.

Datasheet has a plot of expected power detector pin voltage vs output power at different frequencies, but the plot doesn't go as high as I measured. Questionable linear extrapolation gives around 33 dBm output power which is two Watts. -1 dB compression point of the PA is specified to be 34 dBm typical, and it looks like it's in compression as expected.

Calibration

Transmitted waveform.

With matched loads at the antenna connectors I recorded the leakage transmitter signal through the T/R switch. The transmitted waveform is a 100 MHz bandwidth 1 µs long linear frequency sweep with 0.1 of the maximum DAC amplitude.

The baseband frequency sweep signal can be written:

$$ f(t) = \exp\left(j2\pi\left(\frac{B}{2t_s}t\right)t\right) $$

,where $B$ is bandwidth, $t_s$ is the sweep length, $t$ is time, and $j = \sqrt{-1}$.

Received frequency sweep without any correction. 128 overlapping waveforms.

The receiver was set to record 1 µs before and 2 µs after the transmitted signal. 128 waveforms were transmitted with very good repeatability with all of them plotted on top of each other on the graph. Ideally the received signal would be attenuated, delayed and phase shifted copy of the transmitted signal, but there is a clear difference between transmitted and received waveforms.

The non-idealities identifiable from the time-domain data are:

Non-zero DC level before the pulse. This is caused by the DC offset of the ADC.
Spike before 1 µs caused by the transmitter being switched on.
Pulse has DC offset caused by the LO leakage from the transmitter, I signal has higher DC level than Q signal.
Higher baseband frequencies are attenuated more causing a slight drop at the edges of the pulse envelope.
Non-zero DC level after the pulse. Caused both by the ADC DC offset and ADC filter high-pass behaviour.

Compressed leakage signal.

Above is the plot of the pulse compression output of the non-calibrated pulse with -50 dB Taylor window applied to the reference pulse normalized to the peak level. The sidelobe level is -21 dBc, which is far above the ideal level.

The biggest error is caused by the LO leakage from the transmitter. LO leakage from the transmitter is mixed down to DC at the receiver because they share the same LO signal. Since DC level of the balanced linear frequency sweep is non-zero, convolution with the reference sweep gives non-zero result wherever there is a non-zero LO leakage that causes the flat correlation output from 0.5 µs to 1.5 µs.

To improve the sidelobe level LO leakage needs to be compensated. It can be done by adjusting the transmitter waveform so that it has LO signal in opposite phase that cancels the leakage signal. However, before LO leakage compensation ADC DC offset should be compensated since received is used to measure the LO leakage and DC offset of the ADC interferes with it.

DC offset of the ADC is compensated by only triggering the receiver with transmitter disabled. The only signal at the ADC is thermal noise and DC offset. DC level can be measured and subtracted from all subsequent measurements.

With ADC DC offset compensated the LO leakage can be measured by triggering the sweep and outputting only zeros from DAC. Ideally there shouldn't be anything transmitted, but due to LO leakage there is signal transmitted at LO frequency which mixes down to DC at the receiver. DC level of the transmitted signal is adjusted such that the ADC input is zero which results in zero LO leakage.

Compressed leakage signal after LO leakage compensation.

With LO leakage compensation the impulse response looks much nicer. Sidelobe level is -36 dB which is few dB above the ideal -42 dB. There is also a very long -60 dB straight line after the sweep that is caused by the high pass behaviour of the AC coupling capacitors between IQ demodulator and ADC.

Time domain leakage signal with LO compensations. DC level after the pulse is very slightly above zero on I channel.

The reason for the long flat part is that there is a non-zero DC level after the sweep. Baseband frequency sweep has non-zero DC component and when it passes through the high-pass filter it changes the output DC level. Convolution result of frequency sweep with a constant results in non-zero output.

The issue could be reduced by decreasing the high-pass filter cutoff frequency. The AC coupling capacitor is only 100 nF which puts the high-pass cutoff frequency at about 10 kHz. DC offset caused by the high-pass could be also compensated digitally.

The decrease in amplitude as frequency increases is quite clear here. DAC sinc response is compensated digitally, so that isn't the cause for the amplitude drop. The ADC filter was supposed to be quite flat in amplitude, but during manufacturing I had to substitute a different inductor than what I initially chose to use. The substitute inductor has higher series resistance and amplitude isn't as flat. I do have the correct inductors, but I haven't replaced them yet.

50 MHz frequency sweep with 25 MHz offset.

Other solution for the DC offset issue is modulating the frequency sweep so that sweep doesn't include zero frequency, essentially using non-zero IF. Above is time domain plot of received 50 MHz sweep with 25 MHz offset. Frequency sweeps from 0 Hz to 50 MHz compared to -50 MHz to +50 MHz before.

Compressed sweep with offset.

Calculating the pulse compression of the offset sweep gives much cleaner result. The DC offset issue caused by the high-pass filter is completely removed. Sidelobe level is still 2 dB higher than ideal but this is already quite nice looking impulse response. Ideal sidelobes are higher than with 100 MHz sweep because time-bandwidth product is lower and mainlobe is also widened because of the lower bandwidth. The disadvantage of the modulated sweep is that maximum usable bandwidth of the sweep is half of what can be used with a zero centered sweep.

Transmitted signal with Tukey window with α=0.1.

Sidelobes caused by low time-bandwidth product of the pulse can be reduced with transmitted pulse windowing. Window function reduces the effective bandwidth of the transmitted waveform, so it increases the mainlobe width and reduces the range resolution. Transmitter side windowing also decreases the average energy per pulse as the waveform is tapered off at the start and end of the pulse which decreases signal-to-noise ratio. One good windowing function for transmitter side is Tukey window. It just slightly tapers beginning and end of the waveform with middle being at the maximum amplitude. Tukey window has a parameter α that can be used to control how much it windows, with α=0 being equal to no windowing. With α=0.1 the pulse energy, and the receiver SNR, is decreased by 0.8 dB.

Pulse compressed 50 MHz bandwidth pulse with 25 MHz offset frequency, α=0.1 TX Tukey window, and -50 dB RX Taylor window.

Compared to the same pulse without TX window adding Tukey window to the transmitter greatly decreases the far-away sidelobes. At 500 ns offset the sidelobe level has decreased by about 20 dB. The measured sidelobe level is slightly higher than what it should be ideally.

Receiver and transmitter IQ imbalance isn't yet calibrated and there is some frequency dependent distortion from the ADC and DAC filters. However, the current level is good enough for now.

TX noise leakage

If PA is not disabled during the reception noise from PA output leaks into receiver increasing the receiver noise floor.

When switching to reception T/R switch is switched from transmitter to receiver. If PA is kept enabled due to its high gain it has high enough output noise that even when with attenuation from the switch isolation it's still larger than the thermal noise floor of the LNA.

T/R switch can be switched in about 50 nanoseconds but enabling and disabling PA is much slower, it takes about 10 µs. Unfortunately this long PA switching time means that when using a single antenna the receiver noise is higher due to leaked PA noise.

If the input to PA is thermal noise of 50 ohm resistor (-174 dBm/Hz) it's amplified by PAs gain of 32 dB and it adds its own noise to it too. Usually amplifiers noise figure would be reported in the datasheet but this PA doesn't have it listed. PA noise figure can be rather high, 5 - 10 dB wouldn't be too unusual, as they usually aren't optimized to be particularly low noise. With these figures the noise floor at the PA output is about -135 dBm/Hz. T/R switch has limited isolation, exact value for leakage between these ports isn't reported in the datasheet, but 26 dB is the reported typical isolation to the antenna port and isolation between the input ports is usually little better. This means that PA noise at the LNA input is about -165 dBm/Hz which is larger than the thermal noise floor of -174 dBm/Hz and the PA noise limits the receiver performance if it's not switched off.

Noise figure of the receiver is about 5 dB, so the measured noise floor with receiver connected to T/R switch should be about 5 dB higher, instead of calculated 10 dB with noiseless receiver. Actually measuring the ADC noise floor with PA on, when the receiver is connected to T/R switch the noise floor is 2.1 dB higher than when it's connected to the other port. It matches well with the theory considering the big uncertainties in all of the values.

When using two antennas the second receiver switch can be switched to RX2 and the LNA on the RX1 can be switched off which improves the isolation sufficiently that PA leakage doesn't affect the receiver noise.

Target detection

Detecting target from range-Doppler map with CFAR. Range-Doppler map (left), CFAR output (middle), sidelobes filtered out (right). Range on x-axis and Doppler velocity on y-axis.

To get from ADC samples to target detections some more software is required. In general the transmitted signal is a burst of pulses and the first step is to pulse compress each received pulse. After pulse compression the next step is to take FFT over the number of pulses dimension. This sums the power from the different pulses according to velocity of the target. This is called range-Doppler processing and its output is a 2D image with range on one axis and Doppler velocity on the other. Amplitude of each pixel corresponds to the amount of power received at that distance and velocity.

After range-Doppler processing the output is a 2D array of the received power for each range-Doppler bin. To get to target detections we need to identify the bins where there is a target. We also want to separate interesting targets such as moving vehicles from non-interesting targets (clutter) such as sidelobes, trees, ground, and other stationary targets.

The targets in the range-Doppler map could be identified by the amplitude. If a bin's amplitude is high enough above the noise floor then it likely corresponds to a real target and is not just noise. The detection threshold, how much a target needs to be above the noise floor, needs to be chosen to balance false alarm rate and missed detections. In general the noise floor power isn't constant in the range-Doppler map. It can vary as function of time, there can be sidelobes from other nearby targets and clutter, for example ground reflections, can also be considered noise since we don't want to detect each patch of ground as a target. Instead of setting a fixed noise floor it's estimated by averaging nearby bins. For each pixel in the radar map, noise floor is calculated by averaging nearby bins and if amplitude of the bin being tested is larger than threshold times the calculated noise floor then we mark detected target at that location. This is called CFAR (Constant False Alarm Rate) algorithm.

For high amplitude targets there are going to be false detections from sidelobes. After the targets are detected we check if they correspond to a sidelobe of a larger target and unmark it. This is simply done by checking if there is a much larger target in same row or column. Target is also required to have larger amplitude than adjacent bins, this causes only the peak location of each compressed pulse to be detected.

We now have a list of ranges and velocities for detected targets at the accuracy of the radar resolution. Range and velocity measurement accuracy can be improved by interpolating the peak location.

Target tracking

Kalman filter for radar target tracking. Kalman filter predicts the next position of the target from the previous measurements including the uncertainty.

After the detection pipeline we have a list of detections, some of which can be false detections. To be able to track objects in time, detections need to be associated with targets. Kalman filter is used to track each target's position and velocity including uncertainty, and it provides a way to assign each detection to specific target by considering probabilities that detection is from that target.

Tracking uses Stonesoup Python library, which is a library for general object tracking. Specifically radar tracking is heavily based on the StoneSoup tutorial. StoneSoup tutorial explains the tracking well, so I won't repeat it too much here.

The biggest change from the example is that example is for tracking object in 2D with measurement providing it's 2D position but not velocity. Radar measures distance and velocity of each target, but there is no angle information so only 1D tracking is possible.

Transition model for the target is set as constant acceleration. Kalman filter estimates acceleration from the measurements and the next prediction for the target position is made assuming that acceleration is constant.

Radar measurements

Horn antennas. The rust can't be good for efficiency.

I tested the radar by setting the radar on a side of a road and measuring traffic passing by. Pulse length is 2 µs, the bandwidth is 150 MHz, the number of pulses is 1024, RX length is 5 µs with 7 µs delay before the next pulse. I used two antennas with separate TX and RX antenna. Antennas are horn antennas that I made myself.

150 MHz bandwidth corresponds to 1 meter distance resolution. It's important to note that resolution is not the same as accuracy. Resolution is how close two point targets can be to be separated in the measurement. One target can be measured with better accuracy than resolution with accuracy depending on signal-to-noise ratio.

12 µs time between pulses equals 83 kHz pulse repetition frequency. The pulse interval determines the maximum unambiguous target velocity. Velocity measurement is based on measuring phase change between pulses, and if target moves at high enough speed that it moves several wavelengths between pulses, there is no way for radar to know what that multiple is, causing the measured velocity to be ambiguous.

If the target moves half a wavelength between pulses, it causes a full wavelength distance change since the radar pulse goes from the radar to the target and back. At this speed, the phase increases by a full wavelength at each measurement, which looks identical to if the target was stationary. If we don't have information on which direction the target is moving, we also need to consider that a signal increasing 90 degrees in phase every measurement looks identical to a signal that decreases by 270 degrees every measurement. The unambiguous velocity measurement range must be divided by two for negative and positive velocities, resulting in velocity measurement range:

$$v_\text{max} = \frac{\lambda}{4 t_d}$$

,where $\lambda$ is RF wavelength and $t_d$ is pulse repetition interval.

With 5.8 GHz RF frequency and 12 µs pulse repetition interval, the unambiguous velocity measurement range is from -1077 m/s to +1077 m/s. This is over three times the speed of sound, and there won't be any issues with velocity ambiguities when measuring cars.

The Doppler velocity resolution is the unambiguous velocity measurement range divided by the number of pulses, which is 2155 m/s / 1024 = 2.1 m/s in this case. This is the minimum velocity difference that two targets at the same range need to have to be detected as two separate targets. As with the distance accuracy, the velocity measurement accuracy for a single target is better than velocity resolution and improves with signal-to-noise ratio.

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Above is cellphone video synced with a radar range-Doppler map. CFAR detections are plotted as red plus symbols on the range-Doppler map and listed in the order of decreasing SNR on the top right. On the radar image, Y-axis is the Doppler velocity in m/s with negative values towards the radar, X-axis is the distance in meters. The large line at the zero Doppler velocity is reflections from stationary targets.

On the list in the upper right, "frame" is the number of the sweep burst in the radar measurement file, "t" is the time from the first frame, and "detections" is the number of CFAR detections. Detections with a velocity less than 0.1 m/s are filtered out to avoid marking every stationary object as a detection.

Comparing the camera footage to the radar measurements it's easy to correlate the radar detections to cars in the camera footage for close targets. There is some shadowing as cars on the foreground block the view of farther away objects, but the radar is able to detect objects not well visible in the camera footage quite well. The radar can detect cars up to about 400 m, limited by the line of sight. Beyond that the road turns and the view is blocked.

The effect of the DC offset is also visible as very large sidelobes in the range direction. These sidelobes decrease the ability to detect smaller objects near larger ones. Especially towards the end the farthest away car is not always detected by the CFAR as its amplitude isn't sufficiently larger than the sidelobes overlapping it.

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Above is the same measurement, but now with Kalman tracker. The tracker assigns CFAR detections to targets with unique IDs. It's able to track multiple targets, but shadowing and sidelobes cause it to not get enough detections from further away blocked targets, and it loses track of them. The uncertainty in their position increases so much that the track deletion threshold is reached. When they become visible again, a new ID is assigned for them. The tracking software could be improved to reduce this problem, but this is just a testing of the radar and I don't want to spend too much time tuning it for this application.

Received signal. 1024 overlapping pulses. Amplitude is normalized to full-scale.

Above is the received signal of all 1024 pulses from one measurement plotted on the same graph. They overlap very well. There is a small change in the phase during the measurement for moving objects, which is enough to separate the moving objects from stationary ones. There is a large return from leakage and nearby objects at the start, and the received signal from longer time delays that correspond to farther away targets are much weaker.

Low-IF pulse

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While using a large bandwidth sweep centered at DC works, sidelobes caused by the high-pass filter are visible in the results. For second test, I set the RF bandwidth to 75 MHz with 38 MHz modulation frequency so that the frequency sweeps from 0.5 MHz to 75.5 MHz. Other parameters were kept the same.

This time, as expected, the very wide sidelobes caused by the DC offset aren't visible. Range resolution is only half of what is was previously, but it doesn't really cause any issues with tracking of the cars. They are large enough that even with a 2 meter range resolution, there isn't any issues with separating them.

The frame rate is about only half of what is was before. The amount of data should be the same, and I'm not really sure why it's so much slower this time?

At the beginning, a second reflection of the passing car is visible at double the distance and velocity. The radar signal reflects from car, to a sign that is right next to me, back to car, and then is received by the radar. It's much weaker in amplitude and its spread out which causes it to not be detected as a target by CFAR.

In this measurement, there's a cyclist coming towards the radar which is not detected as a target. The reason for it is that the cyclist's speed isn't large enough to separate it well enough from the stationary targets. When CFAR target detection is calculated, all of the nearby stationary targets are included in the noise floor calculation for low-speed targets. The large noise floor causes that the small radar cross section of the cyclist isn't sufficiently above the noise floor to be detected.

For this application, a higher RF frequency would be beneficial. Doubling the RF frequency would double the Doppler velocity bin separation and decrease the maximum unambiguous Doppler velocity by two. Common police radar speed guns operate at around 10 to 35 GHz, although nowadays lidar, which operates near visible light, is starting to be more common for traffic monitoring.

SNR of detected objects as calculated by CFAR vs distance.

SNR of the radar detections is quite good at this range. The maximum SNR at 450 m distance is around 35 dB, while just farther away at 550 m there are no detections. This is because of line of sight, there is no clear path beyond 450 m. Radar SNR should decrease as fourth power of distance, which corresponds to 12 dB drop when the distance is doubled. The radar should be able to detect traffic at even longer distances if there is a clear line of sight.

From this measurement, it isn't clear if the radar link budget is as good as designed, since the radar cross-section of the targets isn't known. Even a typical car cross section can vary a lot depending on the model and the look angle. The radar link budget could be verified by measuring a target with a known radar cross section, typically a corner reflector. However, I don't have a corner reflector. It wouldn't be too difficult to make one with few triangular pieces of PCB, and it just would require some effort.

Full range-doppler map.

The unzoomed range-Doppler map shows how small the view on the videos is on the Doppler axis. The maximum unambiguous velocity is over 1000 m/s. On the range direction, negative distances correspond to pulses that arrive before the start of the transmitted pulse. There shouldn't be any signal there except for sidelobes from targets at positive distances. The noise floor drops at the edges of the range direction because of zero padding in pulse compression.

Single antenna

The previous measurements were made with two antennas, one transmitting and the other receiving. In the next measurement, I have only one antenna that is switched between transmit and receive modes. The pulse was set to the same parameters as the low-IF measurement, except for pulse length, which was decreased from 2 µs to 1 µs to improve detection of close objects.

With one antenna, receiver can only be switched on at the earliest just after the end of the transmission. 1 µs at the speed of light is equal to 300 meters, but radar signal needs to travel to the target and back, so minimum distance to receive the full pulse is 150 meters. However, while it isn't possible to receive the full pulse from shorter distances, it's possible to receive a partial pulse. Pulse compression with only a partial pulse reduces distance resolution and SNR, but it should allow detecting targets at much lower distances.

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Targets below 150 m distance can be detected but the range resolution worsen quickly to unusable levels. Minimum range that radar can detect targets with these settings is about 40 m. In this plot marker is drawn on the tracker predicted location instead of CFAR detections as before.

The tracker parameters were tuned a little bit for this measurement and the tracking performance is better than in the earlier measurements.

Conclusion

Schematic of the radar.

Schematic of the radar is available. It should be useful for also as a software-defined radio with some modifications or reference for other applications that require FPGA. Firmware and software isn't available at the moment, since I'm not sure if I should make those public.

Cost was 330 USD for PCB manufacturing and assembly of two PCBs and additional 225 EUR (240 USD) for components from Digikey that I soldered myself. This is including 24% VAT and shipping costs. There aren't any similar commercial pulse compression radars in the same price range and even software defined radios with similar RF bandwidth are much more expensive.

The designed radar is fundamentally similar to modern large radars. It utilizes digital signal processing, supports arbitrary waveforms and has very large maximum unambiguous target Doppler velocity due to high pulse repetition frequency. Only the maximum range is shorter than large radars due to low output power and small antenna.

Identifying Stable Diffusion XL 1.0 images from VAE artifacts

2023-07-30T00:00:00+03:00

Introduction

The same picture decoded with SDXL-VAE 0.9 (left) and 1.0 (right). Green and violet horizontal artifacts are visible near edges with the 1.0 VAE. Zoomed x8 from the original image.

Lately AI generated images have been getting so good that they are hard to distinguish from real photographs. Some of fake AI generated images have gone viral on social media with some users thinking they are real. Some notable examples are Pope wearing puffer jacket and Trump being arrested. There has been discussions on if AI generated content should be required to be clearly identified by law. Currently many of the big companies building these AI tools are trying to make sure that their tools are used responsibly by watermarking the outputs or limiting what the tools are able to do.

The new SDXL 1.0 text-to-image generation model was recently released that is a big improvement over the previous Stable Diffusion model. When the 1.0 version was released multiple people noticed that there were visible colorful artifacts in the generated images around the edges that were not there in the earlier 0.9 release limited to research use. The cause was determined to be VAE (Variational autoencoder) neural network that is responsible for encoding and decoding the input and output images to latent space that the diffusion u-net works with. The VAE encoder takes as input an RGB image and compresses it to latent space with 1/8 of original resolution with four channels. This smaller dimension makes the diffusion u-net more efficient. VAE also includes a decoder that takes the latent space representation and decodes it back to RGB image.

On social media there have been claims that the new artifacts generated by the 1.0 VAE are a watermark for detecting that images are AI generated but the Stability AI staff haven't commented on it. The Stability AI's official code and diffusers library include invisible watermark that is applied to the generated images to mark them as AI generated, this was also included in the earlier Stable Diffusion models. However, because the Stable Diffusion is open source and watermark is not a part of the neural net model and is applied afterwards to generated images it can be easily removed from the program. In fact, two of the most popular UI's A1111 and ComfyUI don't include this watermark and it is not present in the majority of the Stable diffusion images found in the wild.

Initially only SDXL model with the newer 1.0 VAE was available, but currently the version of the model with older 0.9 VAE can also be downloaded from the Stability AI's huggingface repository. The VAE is also available separately in its own repository with the 1.0 VAE available in the history.

SDXL 1.0 VAE changes from 0.9 version

Calculating difference between each weight in 0.9 and 1.0 VAEs shows that all the encoder weights are identical but there are differences in the decoder weights. It makes sense to only change the decoder when modifying an existing VAE since changing the encoder modifies the latent space representation that u-net works with which harms the quality of generated images.

Original image (left), reproduction error of 0.9 VAE (center) and 1.0 VAE (right). 256x256 original resolution.

Decoding 1024x1024 SDXL generated image resized to 256x256 image with both 0.9 and 1.0 VAEs and plotting the difference to the original image shows that in both cases the largest error is around the edges. With 1.0 VAE there is a clear stair case pattern around each edge. If you want you can view the images here: original, 0.9, 1.0.

Difference of 1.0 encoded image to 0.9 encoded image. 256x256 original resolution.

This pattern is clearer when visualizing the difference between 0.9 and 1.0 VAE processed images. There is a clear green and violet pattern around every edge in the image.

PSNR measurement

VAE measurements from SDXL report.

Stability AI published a report on SDXL that includes performance comparisons of VAEs in SDXL and older Stable Diffusion models on few different measures. Since there is a clear visual difference in SDXL 0.9 and 1.0 VAEs there should be also a difference in the objective measurements. PSNR is peak signal-to-noise ratio, it's SNR normalized to maximum signal dynamic range. I downloaded the COCO2017 validation dataset that was used in the report and ran the images through both VAEs and calculated the PSNR values on 256x256 resized images.

VAE	PSNR (dB)
SDXL-VAE 0.9	25.74
SDXL-VAE 1.0	25.37

The 0.9 VAE had higher (better) PSNR than the 1.0 VAE included with SDXL model. There is slight difference compared to the numbers presented in the SDXL report but I assume that is caused by how images are cropped and resized. The newer 1.0 VAE has about 0.4 dB lower PSNR. Stability AI trained a new VAE from scratch for SDXL to only slightly improve the performance compared to SD 2.X VAE. PSNR drop from 0.9 to 1.0 VAE is bigger than the gain in that training.

Identifying SDXL generated images from VAE artifacts

The 1.0 VAE artifacts are so visible that they can be spotted quite easily by just zooming in to the image and examining edges visually. However it's interesting to measure how easily the 1.0 VAE decoded images can be identified. Instead of looking manually at hundreds of images I decided to train a very simple neural network. Code is available at Github.

I first encoded and decoded COCO2017 training set images using 0.9 and 1.0 VAEs with 256x256 resolution and also saving the resized original 256x256 image. Then I trained a very simple neural net consisting of one convolution layer, global max pooling and two layer linear network. This is a very simple neural network and better performance could be obtained with a larger network. Especially the global max operation is problematic since only maximum of each convolution channel over the whole image is available for the linear layers.

class VAEDetector(nn.Module):
    def __init__(self, conv_chs=64, linear_chs=16):
        super().__init__()
        self.conv_in = nn.Conv2d(3, conv_chs, 9, padding="valid")
        self.linear1 = nn.Linear(conv_chs, linear_chs)
        self.linear2 = nn.Linear(linear_chs, 1)

    def forward(self, x):
        z = self.conv_in(x)
        z = torch.max(torch.max(z, -1)[0], -1)[0]
        z = F.relu(self.linear1(z))
        z = F.sigmoid(self.linear2(z))
        return z

Training results. Grey curve is 1.0 VAE detector and blue 0.9 VAE. 1.0 VAE images are much easier to identify.

I trained the model two times trying to predict if image is decoded by 0.9 VAE and the same with 1.0 VAE. The training losses are shown above. The grey curve is trying to classify if the input image is generated by 1.0 VAE and blue the same for 0.9 VAE. Accuracy/train is the proportion of correctly classified samples in a batch and Loss/train is MSE loss. Training 20k steps with batch size of 64 took about 15 minutes on RTX 2080S GPU.

VAE detector	COCO2017 validation accuracy
SDXL-VAE 0.9	82%
SDXL-VAE 1.0	96%

Testing the detectors on COCO2017 validation set at 256x256 resolution shows that the 1.0 VAE encoded images are much easier to detect than 0.9 VAE encoded images 96% vs 82% accuracy. The detector trying to detect 0.9 VAE images also gets quite good accuracy of 82% which shows that even the 0.9 VAE without clearly visible artifacts does have some features in the output that allows the network to detect it. The detection ratio is based on simply rounding the output to zero or one.

A better detector should probably also try to detect the VAE artifacts after the image has been compressed with various image compression algorithms as most of the images on social media where it would be interesting to detect AI generated images are further compressed.

Visualizing the convolution kernels

Since the network is so simple it is much easier to analyze what it's doing compared to huge deep networks. To make visualizations even simpler I trained the network with just 8 convolution output channels instead of 64. The validation accuracy did drop to 90% for 1.0 VAE and 73% for 0.9 VAE indicating that the other 56 convolution kernels are beneficial but most of the work can be done with fewer kernels.

Detector input convolution kernels. 0.9 (left) and 1.0 (right).

The eight input convolution kernels are plotted above for 0.9 and 1.0 VAE detectors. They are quite different and it's clear that 1.0 VAE detector kernels on the right is trying to detect the green and violet horizontal artifacts.

Generalization to larger images

Example SDXL output image decoded with 1.0 VAE. Some artifacts are visible around the tracks when zoomed in.

The training and validation images were all from COCO2017 dataset at 256x256 resolution. These are quite different from typical SDXL images that have typical resolution of 1024x1024. I generated 200 images using SDXL with two different prompts for photorealistic and illustration images that were decoded with both VAEs. Detection threshold was set to 0.5, simply rounding the output to closer detection. The number of false positives and false negatives could be adjusted with different threshold parameter.

1.0 VAE detector identified 187/200 of 1.0 decoded images correctly as being decoded with 1.0 VAE and 198/200 of 0.9 decoded images correctly as not being decoded with 1.0 VAE.

0.9 VAE detector identified only 63/200 of 0.9 VAE decode images correctly. Since 1.0 and 0.9 VAE errors are similar apart from the 1.0 artifacts its not clear what it should report when tested on 1.0 decoded images but it identifies 158/200 of 1.0 decoded images as not being decoded with 0.9 VAE. The performance is much worse than 1.0 VAE detector and below 50% random guessing chance.

VAE detector	LAION aesthetic subset accuracy
SDXL-VAE 0.9	41%
SDXL-VAE 1.0	94%

On a portion of LAION Aesthetic dataset which consists of various images from the internet with different compression algorithms and parameters, the 1.0 VAE detector generalizes much better. In fact the 0.9 VAE detector gets less than 50% them correct that could be achieved with random guessing.

A slightly more complicated network with about the same number of parameters gets over 99% correct when detecting 1.0 VAE images.

It would be interesting to test if a better network trained with various compressed images would be able to detect artifacts from 0.9 VAE decoded images. 1.0 VAE decoded images are clearly easy to detect.

Conclusion

Detecting and marking of AI generated content is currently a hot issue. While Stability AI has not said if the SDXL outputs are watermarked on purpose, SDXL 1.0 neural net generates visible artifacts that makes it possible for generated images be identified with good accuracy with a simple neural network. However they can be identified also quite easily just by looking at them due to how easily visible the VAE artifacts are. The earlier SDXL 0.9 model does not have these same artifacts and identifying images generated by it is much harder.

Radar phase measurements

2023-05-04T00:00:00+03:00

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Introduction

Radar can measure distance, amplitude and phase of the reflected signal. Distance to the target is usually the most important information. For a single measurement phase is not very useful as it wraps around every half wavelength distance to the target. However, with multiple measurements the change in the phase can give valuable information. Radar imaging, both synthetic and real aperture, relies on the phase information for the image formation. From the small phase differences at different locations it's possible to determine the angular location of the target.

By observing the phase of multiple consecutive measurements, very small distance changes can be measured. For example, with 6 GHz frequency the wavelength is 50 millimeters. Since the radar signal travels from radar to the target and back, a change in the distance of half the wavelength is enough to cause the distance traveled by the signal to be full wavelength. If over multiple measurements the phase changes 360 degrees, we can then determine that the distance between radar and target has changed by half wavelength, 25 mm with 6 GHz radar. For one millimeter accuracy we need to be able to measure a phase difference of 14 degrees. This seems very doable accuracy, but what's the limit?

Radar phase measurement accuracy

Let's consider a radar transmitting a linear frequency sweep. It is processed such that the result is an array of complex numbers representing the amplitude and phase of reflections from targets in that range bin. Range bin size is the range resolution of the radar. The amount of noise in one range bin depends on the minimum separable frequency resolution. This frequency resolution comes from the FFT resolution, which is one over the measurement time: $\Delta f = 1/t_s$.

We are interested in the phase measurement accuracy of signal from one target in one range bin. In that range bin we have ideal noiseless signal from the target and some amount of noise that limits the phase measurement accuracy.

If the signal-to-noise ratio of the target is $S$ then we can normalize by the signal and say that the signal is equal to 1 and noise is from complex normal distribution with mean of zero and standard deviation of $\frac{1}{\sqrt{2}S}$ for both real and imaginary components with zero covariance.

Then the question in mathematical terms becomes: what is the standard deviation of the phase of $1+ \epsilon$, where $\epsilon$ is a sample from the complex normal distribution.

Phase of a complex number $z$ can be calculated as $\text{Arg}(z) = \arctan\left(\frac{y}{x}\right)$, where $x$ is real part of $z$ and $y$ is the imaginary part.

$$\text{Arg}(1 + \epsilon) = \text{Arg}(1 + \mathcal{N}(0, \sigma) + j\mathcal{N}(0, \sigma)) = \arctan\left(\frac{\mathcal{N}(0, \sigma)}{1 + \mathcal{N}(0, \sigma)}\right) \approx \mathcal{N}(0, \sigma)$$

The above formula assumes that SNR is large so that $\mathcal{N}(0, \sigma) \ll 1$. Simplification also uses the fact that for small arguments $\arctan(x) \approx x$.

Using the relation of noise standard deviation to signal-to-noise ratio, the result is that the standard deviation of the phase measurement is $\sigma = \frac{1}{\sqrt{2}S}$, where $S$ is the signal-to-noise ratio.

Maximum SNR

Typically, at low signal strength thermal noise of the receiver is limiting the signal-to-noise ratio. At very high signal level this might not be the case. Any non-linearity, for example, from amplifier or ADC compressing, will generate mixing products. Stability of the clocks is also another limiting factor, all real oscillators output frequency drifts slightly.

Using only the radar itself, it's possible to check if thermal noise or other sources are limiting the SNR by pointing the radar at a large target (ceiling in this case) and checking if the noise level at distances where there aren't any targets changes as antennas are covered. If the phase noise is larger than thermal noise then a large target's phase noise raises noise level also at other distances. This doesn't directly tell about the SNR of the phase measurement, since in that case we care about the noise at the same distance the target is while in this measurement we compare signal strength to noise at different distance.

I set the radar to sweep from 5.4 GHz to 6.0 GHz in 1 ms. The target is a ceiling 2.5 m away (including the cable lengths to the antennas). I added attenuators to the TX output to limit RX from saturating. IF sampling frequency was 500 kHz.

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In the above video the radar IF output spectrum is plotted while I cover the antennas. X-axis is distance in meters and Y-axis is amplitude in decibels (arbitrary reference). At the beginning the target amplitude at 2.5 m is about 58 dB while the noise floor at higher frequencies/distances is at around -20 dB. When the TX antenna is covered the received signal strength drops and amplitude of the target decreases by about 30 dB. Noise floor also drops by 10 dB.

-30 dB level is the thermal noise floor and as the reflected signal strength increases some other noise source raises the noise floor. It's unclear what exactly is the source of the noise. Phase noise should be about 10 dB better than this according to simulations, but with sweeping PLL it can be higher than in steady state since phase locked loop is not stabilized. Some non-linearity could also be the cause since received power is quite large.

For the phase noise measurement accuracy, it's important to know that the maximum SNR that can be measured with this radar is about 75 dB with these parameters. Calculating the SNR from variance of the noise in the largest bin also gives similar results.

Measurements

Radar and horn antennas.

Using my homemade FMCW radar I setup it up to measure its phase measurement accuracy in the best possible condition. By pointing the antennas at the ceiling, the received signal strength is maximized resulting in the best possible SNR. Ceiling is also a stable target so that its possible to assume that all the variance in the measurements are caused by the measurement setup. To avoid saturating the receiver I had to add attenuators at the transmitter output.

Rather than increasing the sweep length, SNR can be also improved by averaging multiple measurements. Making measurements faster also has advantage of being able to detect faster changes.

Frequency was swept linearly from 5.4 GHz to 6.0 GHz. The maximum sweep rate is limited by the phase locked loop sweep rate to about 32 µs at this bandwidth. I set the sweep length to 64 µs with 32 µs delay between sweeps for total of 96 µs between measurements giving about 10 kHz measurement frequency.

The phase measurement works by sending one frequency sweep which is mixed against the transmitted sweep in the receiver. The resulting signal is sine wave with frequency depending on the distance to the target. Normally in FMCW radar Fourier transform would be used to get amplitudes of reflections from each distance, but in this case where we are only looking at one distance we can instead calculate only one bin of the FFT. The phase of the resulting complex number is the wanted result.

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In the video above you can see the effect of moving the antennas on the measured phase. At the start is some sinusoidal looking noise with small amplitude due to measurement setup not being completely stable. Below is the picture of the measurement with consistent scale. The noise level is not visible at full scale.

Antenna movement measurement.

Phase accuracy

Radar pointing at ceiling.

Keeping the radar stationary pointing at the ceiling should result in a constant phase with small amount of noise. However, in the above plot there is clearly drift in the measured phase. During the 40 s measurement the phase drifted 1.6 degrees corresponding to distance change of 116 µm. The drift is caused mainly by temperature change, but also by oscillator frequency and supply voltages drifting. If the signal would be constant with white noise, it would be possible to average measurements indefinitely to obtain better accuracy. The drift makes that impossible and after some amount of averaging, the accuracy starts to get worse as the number of averages is increased.

Radar pointing at ceiling, short timescale.

On the short timescale the drift is so small that the white noise from limited SNR dominates the error.

Phase difference between two successive measurements.

Plotting the phase difference between two successive measurements gives very nice looking Gaussian distribution. The standard deviation is 0.00575 degrees. Since standard deviation of difference of two normally distributed variables from the same distribution is $\sqrt{2}$ times higher than single measurement we can calculate that standard deviation of phase in single measurement is 0.0041 degrees. This corresponds to SNR of 80.0 dB.

Allan deviation of phase.

The optimal averaging time can be calculated with Allan deviation. It's most commonly used for clock stability measurements, but in RF electronics it's also used to characterize radiometer accuracy with different integration times. In the above plot is the Allan deviation of the phase measurement. X-axis the integration time and Y-axis gives the standard deviation of noise at that integration time. At low integration times the white noise dominates and averaging measurements increases the measurement accuracy. At high integration times drift starts to dominate and accuracy gets worse. The optimal integration time is around 5 milliseconds (50 measurements), which should give standard deviation of 0.0012 degrees corresponding to distance of 87 nanometers. Difference of two measurements would have error $\sqrt{2}$ times larger of 0.0017 degrees corresponding to distance of 123 nm.

Phase difference between two successive measurements. 50 averages / measurement.

Plotting the histogram of phase difference between consecutive averages of 50 measurements gives the above plot. The calculated standard deviation is 0.0017 degrees as was predicted from the Allan deviation plot.

Light bulb vibration

Phase measurement of radar pointing to ceiling with nearby light bulb on.

While doing the radar measurements I had an issue of extremely small but consistent frequencies in the IF signal. First I thought that it was caused by some timing issue in the radar hardware. For example, a slip of one clock cycle between ADC and PLL sweep starts could cause a phase shift in the recorded signal. However the phase shift was only about 0.04 degrees which is way below what one clock cycle error should be able to cause. After some troubleshooting I found out that turning the lights off would cause the signal to disappear. It turns out that when I pointed the antennas to the ceiling a light bulb was slightly in the antenna beam and the light bulb vibrates extremely slightly with few micrometer displacement due to mains voltage and this small movement is large enough to be detected by the radar. Any other small movements such as just being close to the radar are also highly visible in the phase plot.

FFT of the light bulb measurement.

Taking the Fourier transform of the measurement shows that there are a lot of 50 Hz harmonics which is the grid frequency here.

Conclusion

Radar is commonly known for measuring distance to targets with quite coarse resolution, but using the phase information it can also measure chance in distance extremely accurately. By observing the phase chance of consecutive measurements, movements smaller than 1 µm can be detected in the best case. Phase change can be used to measure small vibrations such as human heartbeat and breathing rate.

MIMO radar antenna arrays

2021-05-15T00:00:00+03:00

Introduction

A radar with one transmitter and one receiver antenna can measure distances to the targets based on the time of flight of the transmitted electromagnetic wave. One transmitter and receiver isn't however enough to measure angle in which the targets are. A simple way to get the angle information is to use antenna with a very narrow beam and mechanically rotate it. Mechanical rotation does have some drawbacks. It requires a large antenna to achieve the narrow beamwidth, rotating the large antenna requires lot of space and the whole field of view can't be imaged at the same time.

Instead of rotating a single antenna, a radar with multiple stationary antennas can be used to generate image of the targets. Phased array radars use multiple antennas to form the radar image without needing to physically rotate. Because the antennas can operate at the same time the image refresh rate is much faster. MIMO radar is phased array radar with multiple transmitter and receiver antennas. The more antennas are used the better the angular resolution of the radar.

I have been working with MIMO radars for few years. When I started I didn't know much about them and there didn't seem to be much of introduction level material at the time. Many of the existing material in my opinion are overly complex and don't give good intuition about the subject. This post is my try to make introduction level article about the MIMO radar antenna array design that I wished I had when I started to design MIMO radars.

Antenna array beamforming basics

Radar works by transmitting electromagnetic waveform from the transmitter antennas which reflects from the targets and is received by the receiver antennas. Based on the time delay between transmission and reception the distance to the target can be calculated. This doesn't give any information about the angle where the object is. To know the angle of the target multiple antennas are needed. The antennas are at slightly different locations and thus receive the signal at slightly different times. Based on the time differences at each antenna the angle of the target can be solved. In practice instead of the absolute time difference, which would required extremely good time resolution, phase of the received signal is used.

Distance of the traveled radar waveform.

If we assume that the target is very far and the angle to the target from each antenna can be assumed to be identical then the distances the radar waveform travels to each antenna is summarized in the above figure. We will also make another assumption that the distance difference to the target between the antennas is less than range resolution of the radar. This assumption simplifies the image formation as all signals will be in the same range bin after the image formation.

The distance traveled by the radar waveform is the distance from TX antenna to target plus distance from the target back to the RX antenna: $r_{tx} + r_{rx1} = 2r_{tx} + d\sin \theta$. With multiple receiver antennas at different distances to the transmitter the radar waveform travels slightly different distance which can be used to solve for the angle of the target.

The received signal from one target at the RX antenna is of the form: $f_{\text{rx}} = A f_{rx0}\exp\left(\frac{2\pi j}{\lambda} d\sin \theta\right)$. $A$ is the amplitude of the received signal, $f_{rx0}$ is the time-delayed transmitter waveform that would have been received at the transmitter antenna. Exponential term is phase shift that depends on the distance to the target $r$ and wavelength of the radiated signal $\lambda = \frac{c}{f}$. Complex numbers are used to make the analysis mathematically simpler, the actually measured signal are of course real valued and only the real part of the expression would be measured.

With one target and two receiver antennas at different distance the angle of the target can be easily determined by comparing phase differences of the received signals at the two receiver antennas. The phase difference of the received signals at two antennas at distances $d$ and $2d$ from the transmitter is $\exp\left(\frac{2\pi j}{\lambda} d\sin\theta\right)$, angle of the target $\theta$ can be easily solved from the expression. For there to be a single solution the distance $d$ needs to be less than $\lambda/2$, otherwise due to periodicity of $\sin$ same phase could be obtained at two or more angles.

Multiple targets

The situation is a little bit harder when there are multiple targets. Reflection signals from the different targets sum at the receiver and only the summed signal can be measured. With one target the amplitude of the signal was the same at all antennas, but with multiple targets this is not necessarily the case.

After the radar waveform $f_{rx0}$ is demodulated from the receiver signals, each receiver's output is of the form $f_{rx,n} = A_n \exp{j \phi_n}$. Matched filtering is the optimal linear filter to determine how likely it is that there is a target at each angle. In this case the matched filter is the signal that would be observed from a single target at the particular angle: $g_n(\theta) = \exp\left(\frac{2\pi j}{\lambda} d_n\sin\theta\right)$.

The target distribution $t(\theta)$ can be calculated as:

$$ t(\theta) = \sum_{n=0}^N f_{rx,n}g_n^*(\theta) = \sum_{n=0}^N f_{rx,n}\exp\left(-\frac{2\pi j}{\lambda} d_n\sin\theta\right) $$

Setting $f_{rx,n} = 1$ we get the target response of a single target at zero angle.

Antenna array detected target response with different number of RX antennas. Half wavelength spacing.

In the above figure are some target responses with arrays having single transmitter and different number of receivers. Many antennas are required to get a decent angular resolution. Even with 16 receivers the -3 dB angular resolution is just 6 degrees.

Sidelobe level could be adjusted by weighting the terms in the sum. Without weighting the first sidelobes are at -13 dB level.

Antenna arrays with multiple transmitters

For the MIMO principle to be possible we need to assume that receivers can separate the signals from different transmitters. If they would transmit at the same time the same waveform they would just sum up at the receivers and they can't be separated. In practice the transmitters could transmit at different times, at different frequencies or the waveforms are orthogonal and correlator at the receiver can separate them.

Two transmitters and two receivers.

The above antenna configuration is similar to the previous one with one transmitter and two receivers, but now a second transmitter has been added at distance $2d$. The TX1-RX1 and TX1-RX2 signals are the same as before and there are also additional TX2-RX1 and TX2-RX2 signals. We can write $r_{tx2}$ as a function of $r_{tx1}$ and distance between the transmitters $2d$ as $r_{tx2} = r_{tx1} - 2d\sin\theta$. The distance from TX2 to target to RX1 can be written as: $r_{tx2} + (r_{tx1} + d\sin\theta) = 2r_{tx1} - d\sin\theta$. Writing the distances to target of all pairs gives the following table:

Antenna pair	Traveled distance
TX2-RX1	$2r_{tx1} -d\sin\theta$
TX2-RX2	$2r_{tx1}$
TX1-RX1	$2r_{tx1} + d\sin\theta$
TX1-RX2	$2r_{tx1} + 2d\sin\theta$

1TX-4RX array

The 2TX-2RX array with four antennas gives identical length differences between the antenna pairs to 1TX-4RX array with five antennas in the above figure. This results in the identical formed radar image. If the TX2 antenna was moved to the same position as RX2 the measured lengths would match perfectly to the 1TX-4RX array. The constant offset in the measured distances doesn't matter for determining the target angle and I didn't draw it like that because figure would have been not as clear.

Using two transmitters we have saved one total antenna. The savings are even bigger with bigger arrays. MIMO array makes independent measurement for each TX-RX pair, while antenna array with only one transmitter can make measurements equal to the number of receiver antennas. For example with 32 receivers and 32 transmitters each TX-RX pair gives independent measurement for total of 32*32 = 1024 measurements. Antenna array with only one transmitter would need 1024 receiver antennas to get the same number measurements and achieve the same angular resolution.

Virtual transceiver array

In the last section 2TX-2RX array was found to behave similarly to 1TX-4RX array when the antenna spacing were as given. If the antenna spacings would have been different they would not have matched. Antenna arrays with a single transmitter are easy to analyze. The problem is how to determine the correct antenna spacings of the MIMO array to match regular antenna array?

To ease the analysis of MIMO arrays it's possible to calculate virtual element positions of the antenna array. Each virtual element is an overlapping transmitter and receiver that only receives its own transmitted signal. This virtual transceiver antenna array is easier to analyze. In practice for each TX-RX pair we place a virtual transceiver antenna at half way between the both antennas.

TX-RX pair and virtual antenna at half-way between them.

In the above picture is a TX-RX pair at distance $d$ and a virtual element half way between them. The TX to target to RX distance is $2r_{tx} + d\sin\theta$. Distance from virtual element to target to virtual element is $2(r_{tx} + \frac{d}{2}\sin\theta) = 2r_{tx} + d\sin\theta$, which is equal to the TX-RX pair.

One important detail about the transceiver elements is that while regular antenna array spacing needs to be less than half wavelength to avoid aliasing, transceiver element spacing needs to be less than quarter wavelength. This is because transceiver element has both transmitter and receiver overlapping. Moving the transceiver element by quarter wavelength away from the target changes the distance to the target by half wavelength.

1TX-4RX and 2TX-2RX antenna arrays with virtual elements.

In the above picture are 1TX-4RX and 2TX-2RX array antenna locations with the virtual elements marked. Despite having smaller physical size and less antennas virtual element places are identical to the 1TX-4RX array.

2D MIMO antenna arrays

1TX-64RX and 8TX-8RX antenna arrays.

In the above figure 1TX-64RX and 8TX-8RX arrays are compared. 8TX-8RX MIMO array has less less antennas, is physically smaller and has the same virtual array as the 1TX-64RX array. 1TX-64RX physical size is 31.5 wavelengths, 8TX-8RX size is sligthly smaller 28 wavelengths. The Y-axis TX to RX distance is arbitrary and doesn't have effect on the target detection. Target response at zero angle is plotted below.

64 virtual element with λ/4 spacing target response at zero angle.

The angular resolution is about 1.6 degrees which starts to be a decent resolution for a radar.

However there is another MIMO array configuration that results in the same virtual array but is physically even smaller. The trick is to split the RX array in two and put them in the opposite sides of the TX array.

8TX-8RX split RX MIMO array.

The 8TX-8RX MIMO array in the above figure results in the exact same virtual array as the two previous arrays, but the physical size is much smaller at only 17.5 wavelengths. This is almost two times smaller than 1TX-64RX array and in fact as the number of elements increases the split RX MIMO array takes only half of the space of equal array with one transmitter.

There are also other possible 8TX-8RX MIMO arrays that have the same virtual array, but they are not as compact as the split RX array. However they might be useful in some situations. In the figure below is one example:

Alternative 8TX-8RX RX MIMO array.

3D MIMO antenna arrays

Previously the antenna arrays have been one dimensional linear arrays, the obtained radar image has distance and azimuth angle to the target. They were called 2D arrays as the radar image is 2D and has no inclination angle (target height) component. To obtain the also the inclination angle and the full 3D position of the targets the antenna array needs to be two dimensional.

Dense 1TX-64RX 3D antenna array.

With one transmitter the receivers need to be arranged in a dense grid in this case 8x8 requiring total of 64 receiver antennas.

Target response of 1TX-64RX 3D array.

The angular resolution is not that good since there is only eight antennas for X and Y directions.

One MIMO array that has the same virtual array can be achieved by arranging TX and RX antennas in perpendicular rows:

8TX-8RX MIMO 3D antenna array.

While this requires less total antennas it doesn't save space. Similar to split RX 2D array the splitting of the antennas can be done with the 3D array to achieve a box shaped array:

8TX-8RX MIMO 3D box antenna array.

The virtual element array is the same as before but now the physical size is smaller. Similarly to the 2D case, as the number of elements increases the side dimensions of box shaped MIMO array are half of the dense receiver array with one transmitter.

The box configuration does have one drawback that in the corners TX and RX antennas need to be very close together, the distance is only 0.35 wavelengths. In practice this can cause issues with large TX-RX coupling.

The box array has a nice property that it can be tiled while still achieving dense virtual element spacing without any gaps or overlapping elements:

Four tiled 8TX-8RX MIMO 3D box antenna arrays.

This is very useful in practice as it gives space to place components in a large array and allows manufacturing the large array with smaller modules.

Non equally spaced MIMO arrays

All of the above arrays resulted in equally spaced virtual array. This is very useful property in practice as it allows using Fast Fourier Transform in the image formation greatly speeding it up. However non-equally spaced array is also possible and it's possible to calculate their responses with the same equations.

8TX-8RX MIMO array with wider split RX spacing.

If the antennas are not at exactly the right places the virtual array won't be uniform.

Target response of the above array.

Larger absolute size of the virtual array leads to narrower main lobe, but gaps in the virtual array increase the side lobe levels.

Randomly placed 8TX-8RX MIMO array.

In the above picture 8TX and 8RX antennas were placed randomly in -2 to +2 wavelength box following uniform distribution.

Target response of the above array.

Characteristic of randomly distributed antennas is narrow main lobe but high side lobe level.

Receiver antenna virtual array

It's possible to also make virtual array of only receiver antennas. In that case virtual element positions are sum of position of each pair instead of average when using transceiver elements. This kind of virtual array is usually more common for example in text books. It doesn't matter which one is used when analyzing the far field radiation pattern, but one case where it makes a difference is MIMO SAR (synthetic aperture array). MIMO SAR virtual array can be calculated by sum of individual virtual arrays only if transceiver elements are used. I also think that transceiver array derivation is mathematically cleaner.

Conclusion

MIMO radar array with $N_{tx}$ transmitters and $N_{rx}$ receivers can achieve angular resolution comparable to antenna array with one transmitter and $N_{tx} N_{rx}$ receivers. With the right antenna distribution MIMO array can be made half the size of regular antenna array while still achieving the same angular resolution.

The code for visualizing the antenna arrays is available here.

Backprojection Backpropagation

2019-10-22T00:00:00+03:00

Introduction

This post is continuation of my previous synthetic-aperture imaging experiments. In the previous post I used omega-k frequency domain algorithm for the image formation and automatic differentiation based autofocusing with Tensorflow. I managed to get pretty well focused images from bicycle mounted radar considering the total lack of any motion recording data. The autofocus algorithm managed to improve it slightly, but it wasn't perfectly focused.

This time I'm implementing time-domain backprojection algorithm. It has slower $O(n^3)$ time complexity compared to $O(n^2\log n)$ of the omega-k, but it makes up for its slowness by its flexibility. Since omega-k is based on FFT it requires the data to be sampled on a straight line with equal spacing. However due to motion errors during the measurement this doesn't hold in practice. By adjusting the phase of the signal it's possible to approximate the signal that would have been recorded in slightly different position, but that approach has it's limits. Backprojection algorithm works with any shape measurement path.

Backprojection algorithm

Let's start the analysis of the algorithm with the radar signal model. My radar is frequency modulated constant wave (FMCW) radar that transmits short frequency sweeps. I won't repeat the derivation from the previous post, you can check it out if you want to see the details and I'll only give the resulting IF-signal for single target:

$$ s(n, \tau) = \exp\left(-j \frac{4 \pi}{c} (f_c + \gamma \tau) d(\mathbf{x}, \mathbf{p}_n)\right), \quad -T/2 < \tau < T/2 $$

, where $c$ is speed of light, $f_c$ is center frequency of the sweep, $\gamma = B/T =$ sweep bandwidth / sweep length $=$ sweep rate, $\tau$ is time variable and $d(\mathbf{x}, \mathbf{p}_n)$ is distance to the target at position $\mathbf{x}$ from the $n$th sweep at position $\mathbf{p}_n$.

Let's define discrete version of the IF-signal $s[n, m] = s(n, m T_s)$, where $T_s$ is the sampling interval.

The simplest way to generate a SAR image of radar measurements along some path is to use matched filtering. For each pixel in the output image it's possible to calculate what the measured IF signal would have been if there was a target at that pixel. Matched filtering the measured signal with the complex conjugate of the expected will give high value when the measurement matches the expectation. Repeating the filtering process for every pixel in the output gives the focused image. In equation form the filtering for one pixel can be written as:

$$ I(\mathbf{x}) = \sum_{n=0}^{N-1}\sum_{m=0}^{M-1} s[n, m] s_\text{ref}[n, m] $$

, where $s_{ref}[n, m]$ is the reference function which is complex conjugate of the expected IF response:

$$s_\text{ref}[n, m] = \exp\left(j\frac{4 \pi}{c}(f_c + \gamma m T_s) d(\mathbf{x}, \mathbf{p}_n)\right) $$

This SAR focusing algorithm gives especially well focused images, there are no interpolation steps, no approximations, it even works for cases where transmitter and receiver antennas are not at the same position. The big problem however is that it's extremely slow. For every pixel in the image it needs to go over every measured data point. For X x Y image and N sweeps each M points long the time complexity is in the order of $O(XYNM)$, or just $O(n^4)$ for short as they all scale linearly as the image size increases.

There is an easy way to speed it up with some slight assumptions about the measurement setup. If the reference function can be factored into two parts each depenging on only $n$ and $m$ then the double sum can be factored into two sums.

$$ I(\mathbf{x}) = \sum_{n=0}^{N-1} \exp\left(j\frac{4 \pi f_c}{c}d(\mathbf{x}, \mathbf{p}_n)\right) \sum_{m=0}^{M-1} s[n, m] \exp\left(j\frac{4\pi}{c} \gamma m T_s d(\mathbf{x}, \mathbf{p}_n)\right) $$

The trick for faster algorithm is using FFT to calculate the inner sum once and then using interpolation to index the right term for the outer sum.

The definition of the inverse FFT is: $S[n, k] = \sum_{m=0}^{M-1} s[n, m] \exp\left(j 2 \pi k m / M\right)$.

To solve for the right index into the FFT we need to solve for $k$ in the equation:

$$j 2 \pi k m / M = j\frac{4\pi}{c} \gamma m T_s d(\mathbf{x}, \mathbf{p}_n) $$

Solving for $k$ and using the fact that $\gamma = B/T$ and $T_s = T / M =$ sampling period gives:

$$ k = \frac{2 B}{c} d(\mathbf{x}, \mathbf{p}_n) $$

The backprojection algorithm can then be written as:

$$ I(\mathbf{x}) = \sum_{n=0}^{N-1} \exp\left(j\frac{4 \pi f_c}{c}d(\mathbf{x}, \mathbf{p}_n)\right) S\left[n, \frac{2 B}{c} d(\mathbf{x}, \mathbf{p}_n)\right] $$

, where $S[n, k]$ is the Fourier transform of $s[n, m]$ along the second axis. A slight complication is that the new index isn't necessarily a whole number and interpolation is required. The advantage of this form is that it completely removes the inner sum and replaces it with FFT calculated in advance. As a result time complexity of the algorithm improves from $O(n^4)$ to $O(n^3)$ and in practice the new form is much faster.

Bistatic correction

During this derivation it was assumed that transmitter and receiver antennas are at the same position, but that isn't exactly the case with my radar.

Radar mounted on the bicycle. Note the separate transmitter and receiver antennas.

As can be seen in the picture above I actually have separate transmitter and receiver antennas. While the error from considering them to be located on the same place isn't that large, it's not insignificant. Compensating for it in the Omega-k algorithm would have been very difficult, but it's trivial in backprojection algorithm. The distance that the radar measures is distance from transmitter antenna to target to receiver antenna. Replacing the distance to the target $p_n$ in the formula with average of distances from receiver and transmitter antennas to the target gives the measured distance.

Velocity correction

During the measurement the distance to the target is actually not constant due to movement of the platform. A correction for the movement was derived in the previous post for Omega-k and similar correction can be derived for the backprojection too.

First we assume that velocity is constant during one sweep, which isn't really unrealistic assumption as the acceleration would need to be absolutely enormous to have any difference in the speed during the short sweep. The second assumption is that velocity towards the target is constant during the sweep, this assumption is equal to only correcting for the first order errors of the velocity. In practice the non-linearity is so small with reasonable speeds that this isn't a large assumption.

Projection of the velocity $\mathbf{v}[n]$ to the distance vector gives the velocity component towards the target:

$$v_p[n] = \mathbf{v}[n] \cdot \frac{\mathbf{x} - \mathbf{p}_n}{\left|\mathbf{x} - \mathbf{p}_n\right|} $$

Distance to the target during the sweep can then be written as: $d(\mathbf{x}, \mathbf{p}_n) + v_p[n] m T_s$.

Substituting the new distance to the reference function gives:

$$ s[n, m] = \exp\left(j\frac{4\pi}{c}\left(f_c d(\mathbf{x}, \mathbf{p}_n) + \gamma m T_s d(\mathbf{x}, \mathbf{p}_n) + f_c v_p[n] m T_s + \gamma m^2 T_s^2 v_p[n] \right)\right)$$

The first two terms are the same as before, and the next two terms depending on $v_p[n]$ are new. The last term with $m^2$ dependence is problematic since it prevents writing the inner sum as FFT. Quadratic term could be ignored since it's typically much smaller than the other velocity term. By dividing the quadratic velocity term with the other term it can be shown that the quadratic term is at maximum $B / f_c$ of the other term. It mostly matters when sweep bandwidth is significant fraction of the operating frequency.

Better estimate than ignoring the quadratic term can be obtained by fitting a linear function to it (Stringham's PhD. thesis). Least square fit of linear function for $m^2$ over interval 0 to $M-1$ can be obtained by minimizing the sum below for $a$ and $b$:

$$ \min_{a,b}\sum_{m=0}^{M-1} \left(m^2 - (a m + b)\right)^2 $$

The solution can be found as $m^2 \approx (M - 1) m - \frac{1}{6} (M^2 - 3M + 2) \approx M m - \frac{M^2}{6}$.

Substituting it into the quadratic term and simplifying gives: $\gamma m^2 T_s^2 v_p[n] \approx \frac{\gamma m T^2 v_p[n]}{M} - \frac{1}{6} \gamma T^2 v_p[n]$

As before the reference function can be divided into two parts and the inner sum can be replaced with FFT:

$$ I(\mathbf{x}) = \sum_{n=0}^{N-1} \exp\left(j\frac{4 \pi}{c} \left(f_c d(\mathbf{x}, \mathbf{p}_n) - \gamma T^2 v_p[n]/6\right) \right) S\left[n, \frac{2 B}{c} \left(d(\mathbf{x}, \mathbf{p}_n) + \frac{f_c v_p[n]}{\gamma}\right) + T v_p[n]\right] $$

In the outer exponential $4\pi\gamma T^2 v_p[n]/6c = 4\pi B T v_p[n] / 6c$ is normally small enough to be ignored.

The difference to the case where radar was assumed to be stationary during the sweep is just a slight adjustment to the index of the $S[n, k]$.

Tensorflow implementation

Implementation of the backprojection was made as a custom operation in Tensorflow with both CPU and GPU support. The algorithm is excellent candidate for GPU implementation as the parallelization is straightforward: each pixel in the image can be calculated independently. Interpolation needed in the indexing of the FFT result is implemented as simple linear interpolation. FFT is calculated with configurable amount of zero-padding to smooth the output and make the interpolation result more accurate. The result is acceptable even with this simple interpolation unlike interpolation in Omega-k algorithm where linear interpolation would cause visible artifacts in the image.

For calculating gradients, a gradient operation also needs to be implemented. Specifically operation calculating the chain rule needs to be implemented. The operation takes as input the accumulated gradient from the earlier gradient operations and calculates the gradient at the inputs of the operation.

Gradients of complex numbers need some care in Tensorflow. Gradient of real function $y(x)$ with respect to $x$ is calculated simply as $\frac{\partial y}{\partial x}$, but the formula is different if the function is complex valued. The short version is that the gradient of complex valued function $f(x)$ with respect to $x$ needs to be calculated as $\overline{\left(\frac{\partial f}{\partial x} + \frac{\partial \overline f}{\partial x}\right)}$, where $\overline \cdot$ is complex conjugate. For more detailed explanation see this discussion. In this case the second term, conjugated partial derivate, is zero and the result is the normal real gradient but conjugated. For simplicity velocity correction terms are ignored but adding them is trivial. Using chain rule gradient of the backprojection for one pixel of output can be calculated as:

$$\frac{\partial I(\mathbf{x})}{\partial \mathbf{p}} = \sum_{n=0}^{N-1} \frac{\partial d(\mathbf{x}, \mathbf{p}_n)}{\partial \mathbf{p}} \exp\left(j\frac{4 \pi f_c}{c}d(\mathbf{x}, \mathbf{p}_n)\right) \left( j\frac{4 \pi f_c}{c} S\left[n, \frac{2 B}{c} d(\mathbf{x}, \mathbf{p}_n)\right] + \frac{2 B}{c} \frac{\partial S}{\partial d(\mathbf{x}, \mathbf{p}_n)}\left[n, \frac{2 B}{c} d(\mathbf{x}, \mathbf{p}_n)\right] \right)$$

The gradient computation needs gradient of $S$. In the forward direction linear interpolation was used to calculate the values in between the sample points and it's natural to use the slope of the linear interpolation to define the necessary gradient.

The gradient operation calculating the chain rule is complex conjugate of the above gradient times the accumulated gradient summed over all the pixels in the image. If $E$ is some scalar output of the graph and $g$ is the accumulated gradient from all the operations after the SAR image formation, the gradient of $E$ with respect to the input positions can be written as:

$$ \frac{\partial E}{\partial \mathbf{p}} = \sum_\mathbf{x} g[\mathbf{x}] \overline{\left(\frac{\partial I(\mathbf{x})}{\partial \mathbf{p}}\right)}$$

Autofocus

With the backprojection and its gradient operation implemented using Tensorflow for autofocusing the generated image is easy. First calculate the SAR image and it's entropy. Entropy of image generally correlates with how focused image is with better focused images having lower entropy. Next calculate gradient of entropy as function of the input position vector using automatic differentation. A small step towards negative gradient vector should decrease the entropy improving the focus of the image. The steps are repeated until entropy doesn't decrease anymore.

In practice there are some slight issues with the above algorithm. If position of every sample can be optimized individually there are too many degrees of freedom. There are many positions for the samples that give a focused image with low entropy, but most of them have some geometric distortions that don't correspond to the actual scene. For example adding any position offset to all of the samples just moves the resulting image. Backprojection algorithm requires specifying the pixel coordinates beforehand and without any constraints the optimizer can just add a large offset to every sample to move all the data out of the scene to minimize the entropy. Some constraints need to be added for the sample positions to make sure that the optimized image makes sense. Almost all SAR data is taken on a straight path with constant velocity, so it's natural to add some constraints to keep the positions close to a straight line with equal spacing.

Autofocused parking lot image with geometric erorrs due to unrestriected sample positions. There is a kink in the image near origin that shouldn't be there.

In the above image is an example of the scene with unrestricted position optimization. The image looks focused but it has severe geometric distortions as the parking spaces should be evenly spaced. See pictures at the bottom on how the image should look like.

I added two extra constraints for velocity. The first adds penalty if the range direction of the velocity is too large and other adds penalty if the azimuth velocity difference to its mean value is too large. With these constraints the geometric errors are avoided in the cases I tested.

Focusing data With 6444 sweeps each with 1000 samples each for 9666 x 1933 pixel output image the FFT based Omega-k takes 56 ms for one forward iteration and backprojection algorithm takes 436 ms. The time-domain backprojection algorithm is almost ten times slower on this dataset but compared to the Omega-k algorithm it's much more flexible. Omega-k algorithm requires the transmitter and receiver to be at the same position and all samples to be recorded on a straight line with equal distance in the direction of movement between them. Time-domain backprojection can focus any kind of measurement configuration with possibly unevenly samples positions and non-colocated transmitter and receiver antennas.

Measurements

For good comparison with the Omega-k algorithm I focused the previously measured data also with the backprojection algorithm. Autofocus was run for 100 iterations.

Parking lot scene SAR image. Click/tap to see the autofocused version.

Above is the image of the parking lot from the same data as I previously used for the Omega-k algorithm post expect that the sampling rate is twice as large as before avoiding some aliasing artifacts from before. Clicking/tapping and holding shows the focused image. The difference the autofocus makes is big and the autofocused image has excellent focusing.

Solved velocity

The solved velocity is almost constant, there are small oscillations in the range direction and some slight variance in the azimuth direction. There are some spikes that correspond to locations where there are large objects that saturate the receiver. This method doesn't seem to give the best results when receiver has saturated, some spreading of the big objects can be seen as a result in the image.

Comparison of backprojection and omega-k with and without autofocusing.

For farther away objects the difference in focusing between the algorithms is big. In the above comparison image both autofocus algorithms improve the focusing for nearby targets, but only backprojection with autofocusing can also focus the farther away targets.

Park scene SAR image. Click/tap to see the autofocused version.

I also redid the other scene I measured the last time. The improvement from autofocus in that scene is also huge especially for objects farther away. The objects farther away are still spread, but I'm not sure if they should be much better than what they are now. There are lot of issues with occlusions in this scene and some far away objects are visible for the radar only for a very short time. See the images in the previous post for the same data focused with Omega-k algorithm.

Comparison to Google maps image of the same location.

Light posts and tree trunks are very visible in the SAR image compared to the Google maps image. Most of the details inside the park in the upper right can't be seen in the SAR image since a metal fence blocks the most of the view from the radar signal.

Conclusion

I implemented a fast GPU based time-domain backprojection algorithm for synthetic aperture radar image focusing with autofocus based on automatic differentiation implemented as custom operation in Tensorflow. The autofocus algorithm gives a big improvement to focusing of the data from my homemade radar without any position measurement. The code is available at my Github.

Synthetic-aperture radar imaging

2019-08-13T00:00:00+03:00

Introduction

Few years ago I did some simple synthetic-aperture radar (SAR) imaging experiments with the second version of my homemade FMCW radar. Since then I made a much improved third version of the radar but didn't do any SAR measurements due to the amount of effort it would have required. I did have plans to do some SAR experiments afterwards but it took until now to have enough time and motivation.

Synthetic aperture radar (SAR) imaging is a way to synthesize very large antenna array by moving single antenna on a known path. If there are no moving targets in the scene then one radar taking many measurements along a path gives the same result as one ridiculously large radar that is as long as the movement path.

SAR imaging of a single target. As the radar moves the measured distance follows a parabola.

If we move on a straight path while radar pointing 90 degrees from the direction of the path measures a distance to the single target, we will find that the measured distance follows a parabola. This follows directly from the Pythagorean theorem. The SAR imaging problem is finding out the target position from the measured distance data. Of course in a real scene we have multiple targets and the solution isn't as simple as looking where the closest approach is as could be done in the picture above.

Omega-k algorithm

There are few different algorithms for solving this problem, but the one I'm going to use is called Omega-k algorithm. It is a fast imaging algorithm utilizing FFT which also makes it efficient to calculate on GPU. The derivation mostly follows a paper by Guo and Dong.

The radar I have is a frequency modulated constant wave (FMCW) radar. It transmits a short frequency sweep. The transmitted waveform can be modeled as:

$$ s_t(\tau) = \exp(j 2 \pi f_c \tau + \pi \gamma \tau^2),\quad -T_s/2 < \tau < T_s/2 $$

, where $j = \sqrt{-1}$, $f_c =$ RF carrier frequency, $\tau =$ time variable, $\gamma = B/T_s =$ sweep bandwidth / sweep length $=$ sweep rate.

The transmitted wave reflects off a target at some distance and is received after time $t_d$. Ignoring the amplitude, the received wave is a time-delayed copy of the transmitted signal: $s_r(\tau) = s_t(\tau - t_d)$. Signals from multiple targets are summed.

The receiver mixes the received signal with the transmitted signal. This mixing is called dechirping and it removes the high frequency RF component. The result is a low frequency signal, usually some few kHz to MHz and is easy to digitize with low-cost ADC. With the complex signals we take complex conjugate of the transmitted signal to get the low-pass product and the resulting mixing product is:

$$ s_{\text{IF}}(\tau) = s_t(\tau - t_d) s_t^*(\tau) = \exp(-j 2 \pi f_c t_d - j 2 \pi \gamma t_d \tau + j \pi \gamma \tau^2) $$

During SAR measurement the radar repeats this measurement while moving on a straight path with a constant speed. The position of the radar on the path is: $x = v \tau + x_n$, where $v$ is speed of the radar platform and $x_n = v n T_p$. $n$ is the index for measurements and $T_p$ is the transmit repetition interval.

If the radar target is at position $(x_0, y_0)$ the distance to the target can be written as:

$$ R(x) = \sqrt{y_0^2 + (x_0 - x)^2} $$

We set the y-coordinate of the path to be 0 and x position is limited to $-L/2 < x < L/2$, where $L$ is length of the path.

Since electromagnetic waves travel at the speed of light and radar signal needs to travel to the target and back to the radar, we get expression for received signal time delay $t_d = 2R(x)/c$, where $c$ is the speed of light.

The recorded signal can be written as:

$$ s_{\text{IF}}(\tau, x) = \exp\left(-j \frac{4 \pi}{c} (f_c + \gamma \tau) R(x)\right) \exp\left(j \frac{4 \pi \gamma^2}{c^2} R^2(x)\right) $$

The last term in the above expression is called residual video phase term and it's an undesirable by-product from dechirping operation. It should be removed before further processing by multiplying by $\exp(-j \frac{4 \pi \gamma^2}{c^2} R^2(x))$. However this form is inconvenient because it depends on $R(x)$. Using the fact that $R(x) = c t_d / 2$ and that $t_d$ can be expressed in terms of frequency of the IF signal: $f = -2 \gamma R(x) / c = -\gamma t_d \Rightarrow t_d = -\frac{f}{\gamma}$ we can write the correction term as $\exp(-j \pi f^2 / \gamma)$. This form can be applied easily to the Fourier transformed signal.

With RVP term removed the signal is:

$$ s(\tau, x_n) = \exp\left(-j \frac{4 \pi}{c} (f_c + \gamma \tau) \sqrt{y_0^2 + (x_n - x_0 + v \tau)^2}\right) $$

Ideally we would like to have the signal in form $\exp(-j 2 \pi f_y y_0)\exp(-j 2\pi f_x x_0)$, then we could apply two dimensional inverse Fourier transform to get a delta function centered at $(x_0, y_0)$ focusing the image. Currently the signal $s(\tau, x_n)$ is not in this form and inverse Fourier transform doesn't give anything interesting. We need to find some processing steps to apply to the signal to get it to the required form so that inverse Fourier transform can be applied. The reason to look specifically for this kind of form is that FFT can be performed very efficiently.

As a first step, note that $\gamma$ has units of Hz/s and $\tau$ has units of s. The product $\gamma \tau$ has units of Hz so it's a frequency. This product is actually instantenous modulation frequency of the sweep. We do substitution $\gamma \tau \rightarrow f_\tau$ to get rid of the time variable. $\tau$ range was $-T/2 \ldots T/2$ and the new range for $f_\tau$ is $-B/2 \ldots B/2$.

$$ S(f_\tau, x_n) = \exp\left(-j \frac{4 \pi}{c} (f_c + f_\tau) \sqrt{y_0^2 + (x_n - x_0 + \frac{v f_\tau}{\gamma} )^2}\right) $$

Also instead of using frequency the math is cleaner and the implementation of the algorithm is easier when using wavenumbers instead. We define range wavenumber $K_r = K_{rc} + \Delta K_r$. $K_{rc} = \frac{4\pi f_c}{c}$, $\Delta K_r = \frac{4\pi f_\tau}{c} = -\frac{2\pi B}{c} \ldots \frac{2\pi B}{c}$.

$$ S(K_r, x_n) = \exp\left(-j K_r \sqrt{y_0^2 + (x_n - x_0 + \frac{v c \Delta K_r}{4 \pi \gamma} )^2}\right) $$

Next step is to do Fourier transform in azimuth direction (direction of the movement) to move also the $x_n$ variable to frequency domain.

$$ S(K_r, K_x) = \int_{-\infty}^\infty S(K_r, x_n) \exp(-j K_x x_n)\, dx_n = \int_{-\infty}^\infty \exp(j\Phi(x_n))\, dx_n $$

$K_x = 2\pi f_x$ is wavenumber in the azimuth direction. This integral doesn't have exact solution, but there is a method to calculate quite accurate approximation using a method called principle of stationary phase (PSOP). Phase of the function being integrated can be written as:

$$ \Phi(x_n) = -K_r \sqrt{y_0^2 + \left(x_n - x_0 + \frac{v c \Delta K_r}{4 \pi \gamma} \right)^2} - K_x x_n $$

If we plot the phase $\Phi(x_n)$ for some realistic values we get a plot that looks something like below:

Phase and real part of the function being integrated.

There is one point where derivative of the phase is zero (stationary point) and the function varies slowly, but away from that point the function is highly oscillatory. As we integrate the function the oscillations far away from the stationary point cancel out and mainly the area around the stationary point contributes to the result of the integral.

We can expand the function around the stationary point $\frac{d}{dx_n}\Phi(x_n) \rvert_{x_n=x_n^\star} = 0$, as $\Phi(x_n) = \Phi(x_n^\star) + 0 + \frac{1}{2}\Phi^{''}(x_n - x_n^\star)^2$.

Plugging the Taylor expansion in to the integral we get:

$$ \begin{aligned}S(K_r, K_x) &\approx \exp(j\Phi(x_n^\star)) \int_{-\infty}^\infty \exp\left(j\frac{1}{2}\Phi^{''}(x_n^\star)(x_n-x_n^\star)^2\right)\, d x_n \\ &= \exp(j\Phi(x_n^\star)) \int_{-\infty}^\infty \exp\left(j\frac{1}{2}\Phi^{''}(x_n^\star)s^2\right)\, d s \\ &= \exp(j\Phi(x_n^\star)) \sqrt{\frac{2\pi j}{\Phi^{''}(x_n^\star)}} \end{aligned} $$

Since $\Phi(x_n)$ is purely real function, if $\mu$ is sign of the $\Phi(x_n^\star)$, then the square root term can be written as $\sqrt{\frac{2\pi}{|\Phi^{''}(x_n^\star)|}} exp(j\pi \mu/4)$. The second derivative contributes amplitude term and constant phase term, neither of them which is important for focusing image which mainly depends on aligning the phases. We have ignored the amplitude since beginning and it ends up being slowly varying function so we will just approximate it away.

The stationary point of the function $\frac{d}{dx_n}\Phi(x_n) \rvert_{x_n=x_n^\star} = 0$ can be solved to be:

$$ x_n^\star = x_0 - \frac{K_x y_0}{\sqrt{K_r^2 - K_x^2}} - \frac{c \Delta K_r v}{4\pi\gamma} $$

Plugging in the stationary point to the $S(K_r, K_x)$ equation above we get the solution of the integral:

$$ S(K_r, K_x) \approx \exp\left(j(-y_0 \sqrt{K_r^2 - K_x^2} - K_x x_0 + \frac{c \Delta K_r K_x v}{4\pi\gamma})\right) $$

The last term is phase offset caused by the movement of the radar during the sweep. It can be removed by multiplying with exponential in the opposite phase.

$x_0$ term is already in the correct form as it is multiplied only by $K_x$, but $y_0$ term depends on both $K_r$ and $K_x$. $K_r, K_x$ dependence can be fixed by making a substitution $\sqrt{K_r^2 - K_x^2} \rightarrow K_y$. This step is called Stolt interpolation as it is implemented by interpolating the data to a new grid.

After the Stolt interpolation the signal is in form:

$$ S(K_y, K_x) = \exp(j(-K_y y_0 - K_x x_0)) $$

Taking 2D inverse Fourier transform gives the focused image with delta function centered at $(x_0, y_0)$.

Tensorflow implementation

The Omega-k algorithm is mainly large FFTs and interpolation. Both can be implemented well on GPU which requires large parallelism from the program. Well written GPU implementation should be several times faster than CPU implementation. For convenience I'll implement the algorithm using Tensorflow library. Although it's most often used for training neural nets it can just as well be used for other purposes.

The derivation above was done using continous signals but in practice the radar samples the signal with ADC resulting in discrete samples. Most of the above derivation is still valid, some additional thought is needed for example in making sure that sampling grid is small enough to avoid aliasing.

First let's define some parameters.

import numpy as np
import tensorflow as tf

# Load captured data and parameters from the disk.
data, settings = load_data(...)

# 'data' contains the captured data in 2D array. 
# First dimensions is index of the sweep on the path 
# and second is raw values of the sweep from ADC.

# Platform movement speed during the measurement.
v = settings['v']
# Samplerate of the digitized signal.
fs = settings['fs']
# Sweep length.
tsweep = settings['tsweep']
# Bandiwdth of the sweep.
bw = settings['bw']
# RF center frequency of the sweep.
fc = settings['f0'] + bw/2
# Time between the sweeps.
tdelay = settings['tdelay']
# Sweep rate.
gamma = bw / tsweep
# Number of captured sweeps.
sweep_samples = len(data[0])
# Position difference between the captured sweeps.
delta_x = (tsweep + tdelay) * v

# Wavenumber axes
kx = np.linspace(-np.pi/delta_x, np.pi/delta_x, len(data))
dkr = np.linspace((4*np.pi/c)*(-bw/2), (4*np.pi/c)*(bw/2), sweep_samples)
kr = (4*np.pi/c)*fc + dkr
ky0 = (kr[0]**2 - kx[0]**2)**0.5
ky_delta = kr[1] - kr[0] # Same spacing as kr to avoid aliasing during interpolation.
# Ky axis after interpolation.
ky_interp = np.arange(ky0, kr[-1], ky_delta)

Straight away one difference between the real data and the derivation is that my radar doesn't have IQ sampling and the captured signal is purely real. We can however easily generate the required imaginary part. If we take FFT of the captured signal, since the signal is purely real positive and negative frequency components are complex conjugates. However the complex signal should only have negative frequency components (Negative because the delayed RF signal in the receiver mixer is lower frequency than the LO signal). If we zero the positive components and then take inverse FFT, the result is a complex signal with the right properties. This transformation is called Hilbert transform. We can also apply windowing function in range direction and do the RVP term multiplication at the same time. We do this step as a pre-processing step using numpy:

def hilbert_rvp(x, fs, gamma):
    # Last dimension is the range dimension
    y = np.fft.fft(x, axis=-1)
    y[:,:y.shape[1]//2+1] = 0 # Zero the positive frequencies
    # Residual video phase term compensation
    f = np.linspace(-fs/2, fs/2, y.shape[1])
    y *= np.exp(1j * np.pi * f**2 / gamma)
    return np.fft.ifft(y, axis=-1)

# Windowing function in range direction.
# Decreases sidelobes from FFT.
w = np.hanning(data.shape[1])
# fs = Samplerate of the ADC.
# gamma = Sweep bandiwdth / length of the sweep.
data = hilbert_rvp(w * data, fs, gamma)

The next step would be azimuth FFT but before that we will first zero pad the data in azimuth direction because target azimuth positions can be outside the endpoints of the movement path. Without zero padding those targets would alias to locations inside the path.

# Add 'zpad' zeros symmetrically to both sides of the azimuth axis.
data = np.pad(data, ((zpad//2, zpad//2), (0, 0)), 'constant')

Now the pre-processing is done and the rest is done on GPU. The first step is azimuth FFT which needs to be done in a slightly roundabout way due to limitations of the function.

# Create a tensor from pre-processed data.
img = tf.constant(data, dtype=tf.complex64)

# Tensorflow FFT doesn't have option to choose the axis to transform
# and it always calculates FFT over the last axis.
# Transpose to swap the axes before and after FFT to calculate FFT over
# the first axis.
img = tf.transpose(img)
img = tf.signal.fft(img)
img = tf.transpose(img)

# Shift frequency components so that zero-frequency is at the center.
img1, img2 = tf.split(img, [img.shape[0].value - img.shape[0].value//2, img.shape[0].value//2], axis=0)
img = tf.concat([img2, img1], axis=0)

Matched filter is used to correct for movement of the radar during the sweep.

# Matched filtering to compensate for movement during the sweep.
mf = tf.exp(j * tf.cast(tf.expand_dims(dkr, 0) * tf.expand_dims(kx, -1), tf.complex64) 
              * tf.cast(c * v / (4 * np.pi * gamma), tf.complex64))
img = img * mf

After matched filtering we are supposed to do the Stolt interpolation. The data is currently defined on $K_x, K_r$ axes and we need to interpolate it to $K_x, K_y$ axes. In general the new $K_y$ axis points don't correspond exactly to the points on the existing grid and we need to interpolate. The problem is that there is no easy way to do the interpolation in Tensorflow. Simple interpolation methods such as linear interpolation, while easy to implement, are not good enough as they cause distortions in the frequency domain. The ideal interpolation would be sinc interpolation, but the formula needs multiplication for every sample in the signal to calculate one output point resulting in a very slow $O(n^2)$ algorithm. A good compromise between efficient algorithm and minimal frequency domain distortions is Lanczos interpolation. Instead of interpolating with $\text{sinc}(x)$ that has infinite support, a kernel $L(x)$ with finite support is used so that only nearby samples need to be considered in the interpolation:

$$ L(x) = \begin{cases} \text{sinc}(x)\, \text{sinc}(x/a) & \text{if}\ -a < x < a, \\ 0 & \text{otherwise} \end{cases}$$

As far as I know there isn't really any easy way to implement it efficiently in Tensorflow with the existing operations. Applying the formula for every point in the image adds so many operations to the computation graph that it never finishes. I ended up writing a custom operation in C++ for it with both CPU and GPU implementations. The code for it is too long to include here but you can find it in the Git repository. After compiling the operation and writing some Python code to interface with it the Stolt interpolation can be written in a single line:

from interp_op import stolt_interp

# The original grid where the data is defined.
ky = tf.constant((kr**2 - (kx**2)[:,np.newaxis])**0.5, dtype=tf.float32)
# Stolt interpolation
# 'interp_order' is Lanczos kernel order 'a'.
img = stolt_interp(ky, img, ky_interp, interp_order)

The last step is to do 2D inverse FFT to generate the image:

img = tf.signal.ifft2d(img)

Measurements

Radar mounted on the bicycle.

I mounted the radar on the rear rack of bicycle and pedaled the bicycle in a straight line with constant speed to take the measurement. It's very important that the path is known since any difference in the actual position and the one used during the image formation leads to image quality degradation. The position should be known within a fraction of wavelength to avoid any defocusing errors. My radar works at 6 GHz which works out to few cm precision requirement over about 200 m long path. This is probably not going to happen, but we are going to see later how the introduced position errors can be at least partly corrected.

Photograph of the scene being imaged. Imaging path is on the footpath on right and the radar points to the parking lot on left.

In the above picture is the scene being imaged. It's a parking lot with lot of pole-like targets that should be well visible in the generated image.

Raw data without any processing looks like this.

Raw captured data doesn't look like much. Sweep length is 1 ms, with 1 MHz sampling rate, so each sweep has 1000 points and there are total of 6444 sweeps. The output signal of the FMCW radar is a superposition of sine waves from each visible target. Frequency depends on the distance to the target, closer it is the lower the frequency. Amplitude depends on the amount of power reflected which depends on the size, shape, material and distance to the target.

Taking FFT in range direction turns it into easier to read format with range on X-axis.

Above is FFT of the raw data in range direction. Range FFT is not part of the image processing, but this is how non-imaging measurement would be processed. FFT allows changing X-axis from wavenumbers to distance to the target.

Running the Omega-k algorithm for the data generates the following image:

Generated SAR image of the parking lot. The camera photograph above was taken at (90, 0) looking towards (0,0).

The image is mostly focused, there is some visible spreading but at least most of the targets can be recognized. There are some curved artifacts that I'm not sure where they come from.

Generated SAR image of the parking lot. Zooming into the foreground.

When zooming into the foreground objects some smearing from movement deviations is visible. These can be fixed with autofocusing algorithm.

Image formation time on different programs using the above data from the parking lot. Program start-up and data preprocessing time is not included.

There is absolutely huge speed up from utilizing GPU. Numpy implementation does the FFT using Numpy and Stolt interpolation is coded in Python without vectorization. Numpy version takes 22 min and 30 s to form the image of the above data most of which is spent in the interpolation routine. TensorFlow CPU implementation calculates everything on CPU, Stolt interpolation is a custom op coded in C++. It is about 16x times faster than the Numpy implementation with most of the speedup coming from the much faster C++ interpolation function. Image formation takes 1 min 20 s.

TensorFlow GPU Python code is completely identical to the CPU version. It calculates FFTs using nVidia's cufft library on GPU and interpolation is done using custom CUDA kernel also on GPU. Image formation takes only 80 ms. The speedup is absolutely huge being over 1000x faster than TensorFlow CPU and over ten thousand times faster than the Numpy version.

Speedup from GPU shouldn't really be this much. I think part of the reason is that GPU implementation using nVidia's libraries is much more optimized than whatever CPU implementation TensorFlow uses. CPU FFT doesn't seem to be multithreaded, so just multithreaded FFT should speed it up by some small factor.

Minimum Entropy Autofocus

There are some inevitable motion errors when moving the radar on a bicycle. If there is a small deviation in direction of the antenna (Orthogonal to the movement path) it results in phase shifting the signal. If movement errors are known they can be corrected before the image formation by phase shifting the signal in the opposite direction by the equal amount. We don't know the errors but we can use TensorFlow to find the phase shift that minimizes some objective function that corresponds to how well the image is focused.

Comparison of the scene with and without added phase errors. The original scene that is visibly better focused also has lower entropy.

One objective function that corresponds with focusing of the image is entropy calculated as $-\sum_{i} p_{i} \log(p_{i})$, where sum goes over all the pixels in image that is normalized so that all pixels sum to one and are in range $[0, 1]$.

Autofocus can be implemented simply in the code by phase shifting the measurement data at the beginning and adding optimizer that tries to minimize the entropy:

# Define variable.
phase = tf.get_variable("phase", data.shape[0], dtype=tf.float32,
                        initializer=tf.zeros_initializer())

# Also pad the phase when padding the measured data.
phase_padded = tf.pad(phase, [[zpad//2, zpad//2]], 'constant')

# Apply the phase correction.
img = img * tf.exp(j * tf.cast(tf.expand_dims(phase_padded, -1), tf.complex64))

# Rest of the imaging
...

# Entropy calculation
abs_img = tf.abs(img)
abs_img = abs_img / tf.reduce_sum(abs_img)
entropy = -tf.reduce_sum(abs_img * tf.log(abs_img))

phase_smoothness = tf.reduce_mean(tf.square(phase[1:] - phase[:-1]))
loss = entropy + 3 * phase_smoothness

# Define optimizer.
opt_op = tf.train.AdamOptimizer(learning_rate=0.1).minimize(loss)

Run the opt_op until the entropy has stopped decreasing and as a result we should have found the phase errors that minimize the entropy. It's not very efficient since this method requires running the image formation several times, but since the GPU implementation is so fast it is not an issue.

I also found out that adding additional loss phase_smoothness that penalizes large discontinuities in the phase results in slightly better quality image.

Entropy during the optimization.

I ran the optimizer for around 100 steps, more than that will still decrease entropy a little but there isn't really any significant visible changes in the image.

Image after autofocus.

Autofocused image background compared to the original.

Difference between original and autofocused images is not huge, differences are mainly bigger around objects that are farther away and are illuminated for longer time.

SAR image compared with Google maps satellite image.

The generated SAR image matches pretty well with Google maps satellite image of the same location. Google data is slightly older and since it was taken the bottom building has been demolished. Cars are also obviously at different places.

Second scene

Photograph of the scene from the start of the track.

I also made measurements of a nearby park. There's a nice flat and smooth sidewalk next to it that allows easy measuring in a straight long line.

Park image after autofocusing.

At the bottom there are some big buildings that occlude anything behind them. The reflection from them is large enough to saturate the receiver resulting in some artifacts. The light poles, street signs and trees on the foreground are very well focused, light poles very far away are spread a lot more. The problem with at least some of the farther away light poles is that they are occluded by other objects most of the time. The farthest light pole around 230 m is only visible for around quarter of the measurement time but even with that amount of observations it should still be sharper if the image was perfectly focused.

Park image foreground objects. Visible image photograph above was taken from bottom left corner looking upwards.

The foreground objects are well focused. Above are some objects that are also visible on the photograph above. The street curb is very reflective due to its shape. Grass and asphalt surfaces have slightly different radar reflectivity and the path to the zebra crossing is visible on the lower left corner.

The biggest issue is the inaccurate position information. Accurate velocity information should allow resampling the measured data to equal spacing and autofocus should take care most of the remaining sideways movement error.

Check out the code at GitHub or read how I made the radar hardware.

Third version of homemade 6 GHz FMCW radar

2017-09-28T00:00:00+03:00

Finished radar boards without antennas.

Introduction

Previously I made a simple frequency-modulated continuous-wave (FMCW) radar that was able to detect distance of a human sized object to 100 m. It worked, but as it was made with minimal budget and there was a lot of room for improvement.

FMCW radar working principle

FMCW radar block diagram

If you have read my previous articles you should know how FMCW radar works, but for completeness sake short explanation is given below:

Frequency Modulated Continuous Wave (FMCW) radar works by transmitting a chirp which frequency changes linearly with time. This chirp is then radiated with the antenna, reflected from the target and is received by the receiving antenna. On the reception side the received signal that was delayed and undelayed copy of the transmitted chirp are mixed (multiplied) together. The output of the mixer are two sine waves that have frequencies of sum and difference of the waveforms. The frequencies of the received signals are almost the same and the sum waveform has frequency of about two times of the original signal and is filtered out, but the difference waveform has frequency in kHz to few MHz range. The difference frequency is dependent on the delay of the received reflection signal making it possible to determine the delay of the reflected signal. The electromagnetic waves travel at speed of light which allows converting the delay to distance accurately. When there are several targets the output signal is sum of different frequencies and the distances to the targets can be recovered efficiently with Fourier transform.

Issues with the previous version

The biggest issue with the previous version was noisy power supplies causing spurs in the received signal, ADC sampling clock not being locked to PLL reference clock and microcontroller being too slow.

To save money I had chosen to use two buck converters to power all the digital and analog components. Even though I chose the switching frequency of the converters to be above the IF frequency, there ended up being some spurs also at lower frequencies. Adding capacitance and swapping the inductors for better shielded ones helped the problem but didn't completely solve it. The proper fix is to add linear regulator after the buck converters to clean up the switching noise.

The problem with separate clocks for ADC and PLL caused the sampling interval of the ADC to vary between separate sweeps. The maximum offset was only +- half a sample and it wasn't a big issue when only doing range measurements. However when trying to measure heartbeat and respiratory rate the added phase noise from the varying sampling interval caused some noise in the measurements. Noisy power supplies also degraded the phase noise performance. The fix for this one is pretty easy: Use the same clock for both ADC and PLL.

The microcontroller I was using was pretty powerful compared to the cheapest 8-bit microcontrollers, but it was hopelessly underpowered to do any kind of digital signal processing. All of processing power and internal memory was spent in getting the samples from ADC to PC through USB fast enough. Sampling speed of the ADC was 10 MHz and because of lack of DSP resources every sample needed to be transferred to PC. Even the samples between the sweeps that didn't have any useful data were transferred to PC only to be discarded later. With more resources it would have been possible to do digital filtering, lower the sampling speed and only transfer the useful samples.

Microcontrollers don't really have enough processing power to do any kind of non-trivial filtering. For example a 100 tap FIR filter requires 100 multiplications and 100 additions for every sample. Even if the multiplication could be done in one clock cycle the maximum sample rate is too low to be useful. The microcontroller should also have enough processing power to transfer ADC samples and do communication and other logic. FPGA works much better for DSP as the operations can be done in parallel.

The last improvement is adding a second receiver antenna. When there are more than one receiver antenna it is possible to determine the direction of arrival of the received signal. If the return signal arrives in angle it is received at different antennas at different times. The different arrival time causes a phase shift in the IF signal which can be used to determine the direction.

Link budget

Since I'm not changing the transmitter, the maximum range performance should be pretty identical to the last version when using the same horn antennas. When smaller patch antennas are used as receiver antennas the range is going to decrease because the gain and efficiency of the patch antennas is smaller.

The maximum range to detect a target can be calculated using the radar equation:

$$ R_{\text{max}} = \sqrt[4]{\frac{P_t G^2 \lambda^2 \sigma}{P_{\text{min}}(4 \pi)^3}} $$

where $P_t$ is the transmitted power, $G$ is gain of the antennas, $\lambda$ is wavelength, $\sigma$ is the radar cross section of the target and $P_{\text{min}}$ is the minimum detectable signal power.

Most of the values are easy to determine, but the minimum detectable power can be tricky. Clearly the minimum power that can be detected depends on the noise level of the receiver. Noise at the receiver input is RF thermal noise, which can be calculated with $kTBF$, where $k$ is the Boltzmann constant, $T$ is noise temperature, $B$ is noise bandwidth and $F$ is the receiver noise figure.

Determining the correct noise bandwidth to be used is critical and easy to get wrong. Noise bandwidth is clearly smaller than the sweep bandwidth since the IF filter filters most of the RF noise out. IF filter bandwidth determines the noise power that makes it to the ADC, but that is not the noise bandwidth to be used since some of the noise can be clearly filtered out after taking the FFT. When FFT is taken of the IF signal the total RF noise is split equally to each FFT bin. Bandwidth of one FFT bin is the noise bandwidth of the receiver and the bandwidth that should be used in the calculation. Bandwidth of one FFT bin depends only of the lenght of the FFT. With FMCW radar FFT length equals length of one sweep, $t_s$ and bandwidth of one FFT bin is $1/t_s$.

With sweep length of 1 ms and noise figure of 6 dB the RF noise floor at the receiver input is -138 dBm. For the signal to be detectable it should be some amount more powerful than the noise. Using 20 dB for the required signal-to-noise ratio gives minimum detectable signal of -118 dBm.

Variable	Explanation	Value
$P_t$	Transmitted power	15 dBm
$G$	Gain of antennas	13 dBm
$\lambda$	Wavelength	5.2 cm
$\sigma$	Target radar cross-section	1 m²

Plugging the values above to the radar equation the maximum range that radar can see a human sized 1 m² cross-section target can be solved to be 320 m. The target size does have a big effect, for example a bird sized target with cross-section of 0.01 m² can be detected only below 102 m. The transmitted power in the table is somewhat pessimistic to include losses from antennas, cables and PCB.

This would be correct for radar looking at air, but when the radar antennas are looking at a low angle there is going to be problem with clutter that can decrease the SNR. When angle of the antennas is low and the radar is on a flat ground there is going to be returns from the ground from basically every range. Returns from other objects such as trees, buildings and other objects can also overlap the target signal decreasing the signal to noise ratio.

Receiver design

Simplified radar block diagram.

The previous range calculation assumed that the receiver has sufficient dynamic range to detect the RF noise floor, linearity is good enough. Care should be taken especially with the dynamic range of the receiver since reflections from targets near the antennas are going to have much larger power than the noise floor and the receiver should be able to resolve both returns at the same time.

Noise figure of the receiver should be kept as low as possible which can be done by choosing a low noise amplifier with low noise figure and high gain. Higher the gain of the LNA is the smaller the noise contributions of the following stages. A drawback of having high gain is that the input compression point is lowered as either the LNA output stage, mixer or IF amplifier starts to saturate earlier due to higher output power of the high gain LNA. If the input compression point is too low receiver can saturate just from the leakage power between the transmission and receiver antennas. In saturation the receiver doesn't work linearly anymore and many harmonics are generated that are detected as false targets. It's very important to avoid saturating the receiver and this is one of the major issues when using single antenna that is shared between transmitter and receiver. Radar with a low input compression point has higher minimum detection distance below which the returns from the targets saturate the receiver. Choosing the LNA gain ends up being a compromise between noise and input compression point.

It's important to also take into account the noise figure of the low frequency amplifier driving the ADC and noise floor of the ADC. Op-amps typically can't be analyzed using noise figure because ports aren't matched to 50 ohms. The right way is to convert the RF noise to V/$\sqrt{\text{Hz}}$. However comparing the input noise voltage density of the op-amp to noise voltage density of 50 ohm resistor gives a close enough value for hand calculations. Usually op-amps have quite high noise figure due to the resistors used to set the gain. NF of ten to twenty dB is usually a good guess.

ADC has quantization noise and input noise that results in limited dynamic range. Datasheet of the ADC lists the SNR which is calculated by measuring a maximum amplitude sine wave, taking FFT and then dividing the signal power by noise power in all other FFT bins. The dynamic range can be increased with oversampling and filtering. The noise floor after taking the FFT is considerably better than the SNR number listed in the datasheet because noise at different frequencies can be separated.

The dynamic range of the ADC with the FFT processing gain can be calculated with:

$$\text{SNR} + 10 \log_{10}(f_s t_s)$$

where SNR is the SNR of the ADC listed in the datasheet, $f_s$ is the sampling frequency and $t_s$ is sweep length. LTC2292 ADC that I used has listed SNR of 71.3 dB and sampling frequency is 40 MHz. This gives ADC dynamic range of 117 dB with 1 ms sweep.

To make sure that the ADC doesn't limit the system performance the RF noise floor after the ADC should be above the ADC noise floor. The input referred RF noise power at the LNA input is $kTBF = kTF/t_s$. This is amplified by the LNA and mixer by $G_{\text{LNA}}G_{\text{mixer}}$. After the mixer the RMS output voltage can be calculated as $V = \sqrt{Z_{\text{load}} P}$, where $Z_{\text{load}}$ is the mixer output impedance (200 Ω on the mixer I'm using). This voltage is amplified by the IF amplifier by $G_{IF}$. Next the RMS voltage should be converted to peak-to-peak value by multiplying by $2\sqrt{2}$ and then referenced to maximum ADC voltage range. Finally by taking $20\log_{10}$ we will get the noise floor in dBFs units (relative to ADC maximum input signal). Putting it all together in one equation gives:

$$ P_{\text{noise}} = 20\log_{10}( 2\sqrt{2}G_{\text{IF}}\sqrt{G_{\text{LNA}} G_{\text{mixer}} kTF Z_{\text{load}}/t_s }/V_{\text{ref}} )$$

Variable	Explanation	Value
$V_\text{ref}$	ADC maximum peak-to-peak voltage	2 V
$G_\text{IF}$	IF amplifier gain	20 dB
$G_\text{LNA}$	LNA gain	20 dB
$G_\text{mixer}$	Mixer power gain	0 dB
$k$	Boltzmann constant	1.38064852×10^-23 m² kg s^-2 K^-1
$T$	Noise temperature	290 K
$Z_\text{load}$	Mixer output impedance	200 Ω
$F$	Receiver noise figure	6 dB
$t_s$	Sweep length	1 ms

Plugging the above values into the equation gives the noise floor as -102 dBFs. This is 15 dB over the ADC noise floor and the receiver performance is not limited by the ADC.

FPGA Digital signal processing

Block diagram of FPGA DSP.

ADC sampling speed is fixed at 40 MHz, but this is much more than needed. IF filter bandwidth is only 2 MHz so from about 2 MHz to 40 MHz there is only noise which should be filtered out. The reason for such high sampling speed is avoiding aliasing and SNR increase from oversampling. Sampling rate needs to be dropped to make the amount of data manageable. Without decimating the data rate would be 120 MBps, which exceeds the USB 2.0 datarate and is very challenging to store anywhere. Dropping the sample rate to 2 MHz and increasing bit resolution to 16 bits results in much more manageable 8 MBps data rate. When samples between the sweeps are dropped the data rate further reduces by ratio of sweep length to time between the sweeps.

Data rate reduction could be obtained by reducing the ADC sampling speed or dropping some of the ADC samples, but these methods don't get the SNR gain from the oversampling. Averaging of the samples could be used, but this corresponds to filtering with FIR filter with constant 1 coefficients and is not spectrally very nice and will cause aliasing. The correct way is to use FIR filters to filter out the frequencies that would alias and then decimating (dropping samples). This method will give the SNR improvement from oversampling and avoids aliasing of higher frequencies.

Frequency response of the first FIR filter.

Big advantage of digital filtering compared to the analog filtering is that it can be made as accurate as needed, it's noiseless and doesn't require any additional hardware. Above is the frequency response of the first 120 tap FIR filter in the block diagram. This high order would be infeasible to make using analog components but digitally implemented it's not a problem. By combining the decimation and filtering the implementation can be made much more efficiently compared to the naive implementation. High order filter has advantage that transition band can be made very small thus resulting in less wasted spectrum.

The two channel 120 tap FIR filter needs 10 DSP slices when decimating at 20. The other filters are implemented as one filter with reconfigurable coefficients and only require 2 DSP slices. All the filters need a total of 12 DSP slices out of 45 available DSP slices on the FPGA I'm using. Amount of DSP slices required could be dropped even further by increasing the clock speed, but there is no need for it since there is still plenty of room left.

Beamforming

Antenna array.

Two antennas receiving a reflection from the same target will have slightly different phase shift on the received signal due to the small angle dependent difference in the distance to the target. The path length difference between the antennas is $d\sin\theta$, where $d$ is the distance between the antennas and $\theta$ is angle of the target. Phase shift of the received signal is $d\sin\theta/\lambda$ where $\lambda$ is the RF wavelength.

If the antenna outputs are just summed together the targets straight ahead will sum in the same phase while the targets from angle where $d\sin\theta/\lambda= -1$ will be summed in the opposite phases and will cancel each other. Angles between these extremes will experience different degrees of interference.

Beam forming can be done by phase shifting the signals before summing them. When the phase shift $\phi$ is chosen such that $\phi = -d\sin\theta$ the peak of the antenna pattern is shifted to angle $\theta$.

To generate multiple beams for generating an image the simple way would be to repeat the summing of signals for different phase shifts. A more efficient way to synthesize multiple beam is possible using Fourier transform. For radar signals we want to first take FFT of the each ADC signal to move to frequency domain. Each bin of the FFT corresponding to different distances has amplitude and phase of the echo signal. Next all the Fourier transformed signals are placed in array and a second FFT is taken across the antenna dimension. This is equivalent to summing the signals with different phase shifts. Zero padding the array before taking the FFT is necessary to get some resolution to the output. Otherwise we would only get same number of beams as there are antennas.

Array factor with two antennas.

Above plot is the array factor of the two antenna array. This is the beam pattern assuming that the antenna patterns is omnidirectional. The pattern of the real array can be calculated by multiplying the array factor with the radiation pattern of single antenna.

Array factor with eight antennas. Hamming window weighthing.

With eight antennas the angle resolution would be much better and of course even more antennas would give even better angle resolution. Eight receiver channels would increase the cost and power consumption by quite a bit, but it would be possible to have eight antennas that are connected to two receiver channels with a switch. All antennas could then be sampled in four separate sweeps.

Because the array beam width with only two antennas is so poor it's hard to see the angle information on the plots. The angle visualization can be improved by multiplying the measurement with a windowing function that is shifted to the peak location. If there is only one target in the range bin it works well, but if there are multiple targets then the peak is somewhere between them and the windowing makes it look like that there is only one target. There are issues especially with walls and other very wide targets that are reduced to one target by the windowing.

Angle windowing function.

Designing PCB

Schematic. Click for PDF.

The PCB was designed for the same OSH park 4 layer process that I have used many times with my earlier projects. It is the only cheap PCB manufacturing process with better material than FR-4. The material is FR408 which is like FR-4, but losses are lower and the relative permittivity is more tightly controlled.

Compared to the previous version the PCB is much bigger. Especially the FPGA requires a huge amount of space. Power supply is more complicated because FPGA requires several voltages and there are now several linear regulators on board to clean up the switching noise. Of course the second receiver channel also takes lot of space.

Some things however are simpler than before. Previously the IF filter had several op-amps and had variable gain. Now there is only one amplification stage, because I actually calculated that multiple stages are not needed. Variable gain has also been removed and instead ADC dynamic range is maximized so that there is enough dynamic range to not need it.

Layout in KiCad.

I placed an SD-card holder on the PCB for use without a PC but I haven't actually programmed the FPGA to use it yet. There are also two headers that are connected to FPGA IO pins. I don't have any definite use for them, but some examples I had in mind are connecting an inertial measurement unit for SAR motion correction, connecting control signals for use without PC and controlling external antenna switches.

Soldering

Applying solder paste with stencil.

Although I tried to keep the PCB simple it still ended up having about 350 components and many of them are in hard to solder packages.

I start with the more complicated top side. I used to solder the bottom side first with some of the previous projects, but it's easier to apply the solder paste on the top side when there aren't any components on the bottom side. The solder paste is applied using a stencil from OSH stencils. I bought a cheaper Polyimide stencil this time instead of more expensive stainless steel one and I have to say that the stainless steel stencil works much better.

Solder paste on PCB.

Components placed on paste.

The empty QFN footprint on the bottom right is for a second IF amplifier stage. I added it just in case, but didn't end up needing it.

After soldering and adding connectors.

Like all my previous projects I soldered the PCB myself using my reflow oven.

Quality wasn't perfect this time and I had to fix some components by hand later.

When there are so many components there are bound to be some that don't get soldered correctly. One of the components was soldered incorrectly probably due to uneven solder paste placement. I fixed this component by hand using hot air.

Antennas

The old horn antennas I made previously.

I have the horn antennas that I made previously, but there are only two of them and they are not very suitable as receiver antennas due to their large size. Because the antennas are large they need to be placed far away from each other. When distance between the receiver antennas is more than $\lambda/2$ the phase shift of the received signals exceeds 180 degrees for some angles. The resulting IF signal is identical to some smaller angle causing aliasing.

Patch antenna

To avoid angle aliasing I made new patch antennas that are placed $\lambda/2$ away from each other. Due to budget constraints, the PCB material is ordinary FR-4. It has high losses at RF frequencies and causes the antenna to have low efficiency. Relative permittivity of the FR-4 is not very well controlled and varies between the manufacturers and different manufacturing runs. Change in the relative permittivity results in shifting of the antenna operating frequency. Unfortunately any better materials are much more expensive. FR-4 PCBs can be had for less than 10 € from China, while the same PCBs with better material would cost at least 100 €.

2x5 patch array (left) and patch fed horn (right). The thin copper sheet horn has taken some damage.

The antenna consists of five patch antennas in a line with the center antenna being fed from SMA connector through a via underneath the board. Compared to a single element patch antenna the five element array radiates much less in the direction of the array, while in the other direction beam width is very similar to one element patch antenna. The antenna is meant to be mounted such that in the horizontal plane there is a wide beam width for good angle coverage and narrow beam width in the vertical direction to minimize the ground returns.

I also made a horn antenna fed by a patch element. Compared to the previous waveguide fed horn antennas the operating bandwidth is much smaller and the efficiency is lower. The advantage is that the construction is much simpler and the antenna is much easier to mount because of its flat bottom side.

Measured patch array and patch fed horn S-parameters.

The measured S-parameters of the antennas look good except that the operating frequency has shifted to lower frequencies. The design frequency was 5 GHz ISM band (5.725 - 5.875 GHz), but the realized operating frequency of the manufactured antennas is about 150 MHz lower. The reason for the frequency shift is different relative permittivity of the substrate material in simulations and manufactured antennas. I made one patch antenna on FR-4 before and I measured that it had relative permittivity of 4.20 which I used for simulating the new antennas. However based on the measurements FR-4 on the new antennas has relative permittivity of about 4.58.

Measurements

Noise floor

Attenuators on transmitter and receivers.

Earlier I calculated that the RF noise floor should be about -102 dBFs. The noise floor can be measured easily by attaching attenuators to transmitter and receiver. ADC noise floor is harder to measure because I can't disable or disconnect the receivers. I could desolder some components or add a short circuit, but I'm not going to bother.

Above is the measured receiver power spectrum in dBFs (relative to the maximum ADC input voltage). Calculation was -102 dBFs and the measurement is -99 dBFs on the first channel and -100 dBFs on the second one. Measurement agrees very well with the calculation considering that the gains of the components can vary few dB.

At low frequencies/distances there is some signals visible. The lowest bin is DC and is probably caused by the IF amplifier and ADC DC offset and FFT windowing. At little bit higher frequencies there are some genuine targets probably from ceiling and walls. If I wave my hand over the radar I can see the targets moving. It seems that the microstrip lines on the board radiate enough that radar can detect some nearby targets without antennas. A similar issue could be seen with my homemade VNA. Unlike with the VNA, isolation is not too important with FMCW radar because it will only cause targets at very low distances.

Park

Image of the scene.

Time-domain plot of the received signals.

Time-range plot captured with the patch antennas. Previous sweep is subtracted from the current one to remove fixed targets.

Above is a time-range plot of me riding a bicycle in a circle in front of the radar. The circle part of course is not visible on this plot as angle of the target is not shown.

Your browser does not support the video tag.

With the added angle dimension visualizing the data now requires a video. Above is a video of the same measurement that was plotted above. This time fixed targets were not removed and lightning posts and trees are visible as fixed targets. Without the angle information the fixed targets would have just cluttered the plot but now the video looks quite clear even without any additional post processing.

You can tell from the video that I start and end the video at left side of the radar (positive cross range). Walking in front of the radar at the beginning shadows the background targets and also causes some clipping at IF due to the strong reflections.

The angle resolution is not that good but this is expected because there are only two receiver antennas. Windowing used for visualizing the angle of target causes the wide bushes at the background seem to oscillate wildly because of small changes in the received reflections. Because returns at different angles are nearly equal small noise can flip the peak to different location.

In the video it's clear that magnitude of reflections around the center is much bigger than at the edges. This is mostly because of the narrow beam width of the transmitting horn antenna. Receiver antennas will also have less gain at high angles further dropping received reflection magnitude.

The lamp posts in the picture are also clearly visible on the video and don't move around as much as the bush. When I go near them in the same range bin the location seems to jump around. The problem is that when I am at the same range as them the angle windowing still assumes that there is only one target and puts the target center somewhere between the lamp post and me.

Your browser does not support the video tag.

Above is the same video as previously, but with the previous sweep subtracted from the current one to remove fixed targets. Subtracting the fixed targets highlights some of the problems with the angle visualization even more.

Traffic speed

Image of the scene.

There was a nice bridge near me that went over a busy road so I decided to test how well the radar can see cars. Cars are have pretty big radar cross section and should be visible very far.

Time-range plot of traffic with fixed targets removed.

The above time-range plot is recorded with a single horn antenna so there is no angle information. Clutter is removed by subtracting the previous sweep from the current one leaving just the moving objects. Without the clutter reduction there are so many targets that it's hard to see anything.

The range was previously cut off because there wasn't any far away targets, but this time I'm plotting the full range. Decimate by two filter was active during this capture to limit the data rate and it limits the range to 250 m with 300 MHz sweep. Without decimating the range would be 500 m, but there isn't much point in capturing that since the line of sight from the bridge is less than that. SNR is still good at 200 m so it should be able to see much farther. At far ranges the drop in SNR is caused by the decimation filter filtering also little bit below the Nyquist frequency to avoid aliasing.

From the plot it can be seen that during the capture there five cars going away from the radar and one car and one bicyclist coming towards. Car speeds can be calculated from the graph by simply dividing the traveled distance by time it took to travel it. There are better ways for measuring the speed, but I'm too lazy to implement them. The solved speeds are around 60 to 70 km/h. The speed limit is 80 km/h so all of them seem to be driving little below the speed limit, but I guess that makes sense as there are traffic lights just after me.

Conclusion

The changes in the newest version fixed the problems in the previous version and the performance of the radar seems very good. Two receiver channels allows determining the angle of the target, but the angle resolution with only two receiver antennas is not too good. The angle resolution is limited by the physics and getting more resolution would need more antennas. Multiple switched receiver antennas are on my todo list.

If you are interested in taking a more detailed look, all hardware design files, firmware and processing software are available at github.

TRL measurements with homemade VNA and open source software

2017-05-08T00:00:00+03:00

Introduction

I have been using the OSH Park's 4 layer process a lot on my own projects. It has FR408 substrate that has better controlled permittivity and lower losses than ordinary FR-4 that other low cost PCB manufacturers use. In my opinion currently it is the best low cost process for making RF PCBs.

My previous boards have worked pretty well, but I decided to make a test board that I can use to characterize the process better.

Test board for TRL calibration.

In the above picture is the test board that I made. It has two 50 ohm microstrip lines of different length, one open microstrip line, one microstrip line terminated with 50 ohm resistor and line with 0402 footprint that I populated with a 1 nF capacitor. I'm using this same type of capacitor as a general DC blocking capacitor in my VNA so I'm interested in finding out how it performs at high frequencies.

Block diagram of the board.

Using this board and TRL calibration, effect of the connectors can be calibrated out resulting in accurate measurements of the transmission line parameters. Accurate measurement of the capacitor is also obtained, which is useful in a system design. Other 0402 footprint passives can also be populated in place of capacitor to measure them at high frequencies.

If you are not familiar with TRL calibration it is a different method for calibrating a VNA. The normal SOLT calibration uses Short, Open, Load and Thru calibration standard measurements and sets the measurement reference plane to the end of the coaxial connector. Calibration standards need to be known accurately or otherwise there will be errors in the measurements.

TRL calibration uses at least two lines of different lengths and one reflect. No short, open or load standards are needed and unlike standards used with SOLT calibration, lines or reflect don't need to be fully known. Line lengths need to be known, but their electrical behaviour doesn't need to be known accurately. Phase of the reflection coefficient of reflect standard needs to be known within +- 90 degree accuracy. Real reflection coefficient and propagation constant of the transmission lines will be solved during the calibration.

After the TRL calibration reference plane is placed after the SMA connectors on the board. The exact reference plane location is in the middle of the shortest line. For example the capacitor test structure on the board would include the SMA connectors if measured using the SOLT calibration, but with TRL calibration the reference planes are right next to the capacitor pads.

There are few limitations on the TRL calibration:

Length difference between the lines should ideally be a quarter wavelength. If the measured phase is a multiple of 180 degrees, the resulting system of equation is singular and calibration fails. This results in a limited bandwidth for the calibration but it can be extended by using multiple lines with different lengths.
Reference impedance of the calibration is the characteristic impedance of the transmission lines and not 50 or 75 ohms as is usual. The measured S-parameters are referenced to this possibly frequency dependent and complex impedance. If the characteristic impedance is not known accurately, the measured results might not be very useful.

Propagation constant

Propagation constant of the transmission line characterizes how phase and amplitude of a wave traveling in a transmission line varies as a function of distance. During the TRL calibration propagation constant is solved and it is one of the outputs of the calibration. Propagation constant varies significantly as a function of frequency and thus can't be really called a constant but that is the established term.

S21 coefficient of a transmission line with length $l$ can be calculated using propagation constant as: $S_{21} = e^{-\gamma l}$, where $\gamma = \alpha + j \beta$ is the propagation constant.

Real part $\alpha$ of the propagation constant causes loss and imaginary part $\beta$ causes phase shift. Units of $\alpha$ are in Nepers/meter, which can be converter to more practical units of dB/m with equation $20\log_{10}(e)\alpha$. $\beta$ includes the frequency dependence and looks like a very steep straight line when plotted as is. It can be normalized by dividing by $2\pi f$, but I think that effective permittivity of the transmission line is a more useful quantity.

Effective permittivity of the transmission line is related to the speed of electromagnetic wave on the transmission line via equation: $v = \frac{c}{\sqrt{\epsilon_{\text{eff}}}}$, where $c$ is the speed of light. Wavelength of the electromagnetic wave in a transmission line can be calculated using effective permittivity with: $\lambda = \frac{v}{f} = \frac{c}{f\sqrt{\epsilon_{\text{eff}}}}$. Since many RF circuits need transmission lines with accurately known length in wavelengths, knowing the effective permittivity accurately is very useful.

Effective permittivity of the transmission line depends on the permittivities of the surrounding materials. With stripline or coaxial cable where the signal conductor is completely surrounded by one material the effective permittivity of the transmission line is equal to the permittivity of the surrounding material. If the TRL calibration would be done for a stripline, the effective permittivity calculated from the solved propagation constant would directly give the permittivity of the material. With microstrip some of the field travels also on the air and the effective permittivity is somewhere between permittivities of substrate material and air. The exact value depends on the line geometry.

Effective permittivity can be calculated from the propagation constant with:

$$ \epsilon_{\text{eff}} = - \left(\frac{\gamma}{2\pi f/c}\right)^2 $$

Measurements

All of the following measurements are done using the second version of my homemade VNA.

Unknown thru

Before doing the TRL calibration let's first do a regular calibration to the SMA connectors to see what the S-parameters look like with the SMA connectors.

I'm using scikit-rf Python library for doing the calibration. In the library there are several possible calibration methods to choose from. There is ordinary SOLT that most of the commercial VNAs have builtin, but also several more advanced calibration routines. This time I'm using UnknownThru calibration, because I know the short, open and match standards I'm using well because I have measured them with a commercial VNA, but I don't have a measurement of the through standard. Unknown thru calibration doesn't requires knowledge of the thru standard S-parameters so it is a good calibration to use in this case.

Below is the code for doing UnknownThru calibration:

import sys
import skrf
#Use skrf plot style
skrf.stylely()

#Load the measured uncalibrated S-parameter files
ll = skrf.Network('load_load.s2p')
oo = skrf.Network('open_open.s2p')
sl = skrf.Network('short_load.s2p')
ls = skrf.Network('load_short.s2p')
through = skrf.Network('through.s2p')

sw_terms = skrf.Network('sw_terms.s2p')
switch_terms = (sw_terms.s11, sw_terms.s22)

#Network to plot
dut = skrf.Network(sys.argv[1])

#Calibration kit measurements
o_i = skrf.Network('../cal_kit/open.s1p')
s_i = skrf.Network('../cal_kit/short.s1p')
l_i = skrf.Network('../cal_kit/load.s1p')

frequency = through.frequency

#Interpolate the calibration standard S-parameters
o_i = o_i.interpolate(frequency)
s_i = s_i.interpolate(frequency)
l_i = l_i.interpolate(frequency)

#Make two-port networks from two one-ports
oo_i = skrf.two_port_reflect(o_i, o_i)
ls_i = skrf.two_port_reflect(l_i, s_i)
sl_i = skrf.two_port_reflect(s_i, l_i)

#Make ideal through Network
through_s = [[[0,1],[1,0]] for f in through.f]
through_i = skrf.Network(s=through_s, frequency=frequency)

cal = skrf.UnknownThru(
        measured = [oo, sl, ls, through],
        ideals = [oo_i, sl_i, ls_i, through_i],
        n_thrus = 1,
        isolation= ll,
        switch_terms = switch_terms
        )

cal.apply_cal(dut).plot_s_db()

The measured networks follow the std1-std2 naming rule, where std1 is the standard connected to port 1 and std2 on port 2. Measurements of open, short and load are needed on the both ports. Standards are usually measured as one port on both ports, but in this case standards are connected to both ports and they are measured as a two port. Through also needs to be measured, but with this calibration real through S-parameters don't need to be known. Through can even be a line on the board being measured or any other transmissive circuit that has S21 equal to S12.

Switch terms are needed to account for reflection coefficient of the port switch inside the VNA that causes different termination depending on the measurement direction. They are measured with the ports connected together using any transmissive standard. They can't be calculated from the S-parameters and instead raw receiver measurements are required. It's not an issue with my homemade VNA since accessing the raw receiver outputs is easy, but it can be tricky with some older VNAs. They can also be extracted from SOLT measurements if the receiver measurements are not possible.

Short line calibrated to SMA connectors.

Close up to S21 of short line.

Above is the shortest 5mm long line on the board calibrated to the SMA connectors. It is matched quite well which suggest that the SMA connector matching is also good and that the line is not at least very far off from 50 ohms. Loss is smaller than 0.5 dB even at 6 GHz.

Solved SMA through S-parameters.

Close up to S21 of SMA through.

Above are the solved S-parameters of the SMA through (right side on this picture) that I used for the calibration. Loss is okay, but matching is not spectacular. I guess the through is not exactly 50 ohms. Same results are obtained if the line on the board is used as a through in the calibration.

Long line calibrated to SMA connectors.

Close up to S21 of the long line.

Longer 18mm line however isn't performing as well as the shorter one. There are resonances at 4.2 and 5.8 GHz causing increased losses. I measured also another identical board and it has the same resonances. I'm not exactly sure why it happens and I haven't investigated it much yet. Maybe the bottom ground plane works as an antenna? Board has 4 layers and the bottom three layers have a ground plane. The two bottom ground planes are connected to the microstrip ground plane only near the SMA connectors and it is possible that the bottom ground plane is resonating.

Series capacitor test structure calibrated to SMA connectors.

Close up to S21 of the capacitor.

Capacitor test structure doesn't have resonance at 4.2 GHz, but maybe there is a small resonance at 5.8 GHz? Compared to the through line, capacitor test structure has little higher losses as is expected.

TRL

There are three different TRL calibrations in the scikit-rf: Ordinary TRL calibration (TRL), Least squares multiline TRL (MultilineTRL) and NIST Multiline TRL (NISTMultilineTRL).

MultilineTRL is just an alias of TRL, but difference between the TRL and NISTMultilineTRL calibrations is that they behave differently when using multiple lines. Ordinary least squares TRL uses the same system of equations with multiple lines as with just one, but solves it with least squares. It is simple to implement but doesn't avoid singularities if any pair of lines has phase difference that is multiple of 180 degrees. NIST multiline TRL combines the lines more intelligently avoiding the singularities as long as there is one pair of lines that has non-singular phase difference. It allows very wideband calibration even with just a few lines if their lengths are chosen correctly.

In this simple case with one through and one line there shouldn't be difference in the accuracy but I'm using NISTMultilineTRL because it has few features that the TRL class doesn't have.

Below is the code for calibrating the uncorrected measurements:

import skrf
import matplotlib.pyplot as plt
#Use the skrf plot style
skrf.stylely()

#Load the uncalibrated S-parameters
trl_thru = skrf.Network('trl_through.s2p')
trl_line = skrf.Network('trl_line.s2p')
trl_open1 = skrf.Network('trl_open_load.s2p')
trl_open2 = skrf.Network('trl_load_open.s2p')
#Assemble the two reflection measurements into same network
trl_open = skrf.two_port_reflect(trl_open1.s11, trl_open2.s22)
trl_dut = skrf.Network('trl_cap.s2p')

sw_terms = skrf.Network('sw_terms.s2p')
switch_terms = (sw_terms.s11, sw_terms.s22)

#Measurement with load on both ports for isolation calibration
ll = skrf.Network('load_load.s2p')

cal_trl = skrf.NISTMultilineTRL(
        measured = [trl_thru, trl_open, trl_line],
        Grefls = [1], #Estimate of the reflection coefficient
        er_est = 3, #Estimated effective permittivity
        l = [0, 13e-3], #Line lengths
        gamma_root_choice = 'real', #Assumes that lines are lossy
        switch_terms = switch_terms,
        isolation = ll
        )

#Plot the calibrated capacitor S-parameters
cal_trl.apply_cal(trl_dut).plot_s_db()

13 mm long line TRL calibration.

The 13 mm long line still has the resonance after the calibration. The resonance will also be visible in all the other measurements since the line with resonance is used in calculating the calibration error coefficients. S11 and S22 are perfect because reference impedance of the TRL calibration is equal to the characteristic impedance of the lines.

Series capacitor test structure calibrated with TRL.

Series capacitor S21 detail.

Above is the capacitor test structure this time calibrated with TRL. With the unknown thru calibration S21 of the capacitor was -0.4 dB at 4 GHz, but with TRL calibration the S21 is only -0.1 dB as the connector losses are calibrated out.

Self resonance frequency of this capacitor is 380 MHz. Equivalent series resistance (ESR) of the capacitor and pads can be determined from the loss at this frequency. Since at self resonance frequency inductive and capacitive reactances cancel out, the capacitor looks like a small valued resistor. S21 of a series resistor can be solved as: $S_{21} = 2Z_0/(2Z_0+ R)$. S21 of the capacitor is 0.022 dB dB at 380 MHz, giving a series resistance of 0.26 Ω assuming 50 ohm reference impedance. But the reference impedance in this measurement is really the characteristic impedance of the lines. It is probably close to 50 ohms, but characteristic impedance needs to be determined more accurately if a more accurate estimate of ESR is needed.

The solved effective permittivity and line attenuation can be plotted with:

plt.figure()
plt.title('Effective permittivity')
plt.xlabel('Frequency [Hz]')
plt.plot(freqs, np.real(cal_trl.er_eff))

plt.figure()
plt.title('Attenuation dB/m')
plt.xlabel('Frequency [Hz]')
plt.plot(freqs, 20*np.log10(np.exp(1))*cal_trl.gamma.real)

Solved effective permittivity.

Solved line attenuation.

The resonance at 4.2 GHz affects both effective permittivity and attenuation, but below 4 GHz both should be correct. Effective permittivity is quite noisy, but it appears to be around 2.84 at high frequencies and more at lower frequencies.

Line attenuation is around 4.3 dB/m at 1 GHz and 11.6 dB/m at 3 GHz. Using a calculator the theoretical values are 4.9 dB/m at 1 GHz and 11.9 dB/m at 3 GHz.

Accuracy of the calibration can be estimated using the normalized standard deviation plot. It is normalized such that when one through and one line calibration is the most accurate, the phase difference is 90 degrees, the normalized standard deviation is one. When the phase difference goes further from 90 degrees accuracy decreases and the normalized standard deviation increases.

plt.figure()
plt.title('Normalized standard deviation')
plt.xlabel('Frequency [Hz]')
plt.plot(freqs, cal_trl.nstd)

Normalized standard deviation.

As a rule of thumb phase difference between through and line should be between 20 and 160 degrees for an accurate calibration. In the normalized standard deviation plot this corresponds to about three. From the above plot it is clear that at around below 500 MHz the accuracy is much worse than this. To improve the accuracy a longer line that is 90 degrees at low frequencies should be added.

Characteristic impedance

Transmission line lumped element model. Source: Wikipedia

Transmission line can be modeled using sections of lumped elements. Each section represents a short section of transmission line. One section has series resistor and inductor and parallel capacitor and conductance.

Using the lumped section model propagation constant of the transmission line can be defined as:

$$ \gamma = \sqrt{(R + j\omega L)(G + j \omega C)} $$

and characteristic impedance as:

$$ Z_0 = \sqrt{\frac{R + j \omega L}{G + j \omega C}} $$

or written using the propagation constant:

$$ Z_0 = \frac{\gamma}{G + j \omega C} \approx \frac{\gamma}{j\omega C} $$

Typically conductance (G) of the transmission line is very close to zero if the substrate is not conductive and it can be approximated to be zero. Because propagation constant is solved during the TRL calibration characteristic impedance of the transmission line can be determined if the capacitance per length of the transmission line is known.

C could be measured directly, but it is hard to measure accurately since capacitance of a typical transmission line is very low. Here is a good paper of the possible methods for measuring it.

Measuring characteristic impedance

There are several ways to measure the characteristic impedance of the microstrip lines. The first most simple way would probably be trying to curve fit to the measured lines, but the problem is that we can't fit to the TRL calibrated measurements because TRL calibration's reference impedance is the characteristic impedance of the lines that we want to measure. Fitting to the measurements corrected to the SMA connectors is possible, but accuracy is limited by the matching of the connectors.

Better method without extra measurements is to first calibrate measurements to the SMA connector for example with unknown thru calibration and then do TRL calibration as a second level calibration. Now the TRL calibration error terms represent the S-parameters of the circuit between the reference planes of the calibrations. Unknown thru reference plane was at the SMA connectors and TRL calibrations reference plane is after the SMA connector on the PCB, thus the error terms of the TRL calibration are the S-parameters of the connector. Port impedances of the error terms are 50 ohm from the unknown thru and characteristic impedance of the line on the TRL side. If the SMA connector is short and well matched then the error terms only include the impedance change. Modeling the error terms as an ideal impedance transformer the TRL reference impedance can be solved. There are even enough degrees of freedoms to add a shunt capacitance to the model and still solve the characteristic impedance. For overview of this method see this paper.

We can get the error parameters of the calibration as follows from the calibration:

s21 = np.sqrt(cal_trl.coefs['forward reflection tracking'])
connector_s = np.array(\
            [[cal_trl.coefs['forward directivity'], s21],\
            [s21, cal_trl.coefs['forward source match']]] \
        ).transpose().reshape(-1,2,2)
connector = skrf.Network(s=connector_s, frequency=cal_trl.frequency, name='SMA')

connector.plot_s_db()

VNA calibration can't solve for both S21 and S12 of the error network and instead only the product S12*S21 is solved, which is called reflection tracking. For passive circuit S12 = S21 and we can take a square root of the reflection tracking to solve for S12 and S21. Taking square root leaves 180 degree phase ambiquity, but that is not important when only looking a the magnitudes. Directivity is S11 and source match is the S22.

SMA connector S-parameters from the error terms.

Above is the plot of the S-parameters of the connector from the error terms. Port 1 is the connector side and port 2 is the board side. Port 1 reference impedance is the reference impedance of the unknown thru calibration which is 50 ohms in this case. Port 2 reference impedance is the TRL calibration reference impedance which is the characteristic impedance of the lines that we don't know. At low frequencies we would expect the connector to be matched well, but S11 is only -22 dB suggesting that characteristic impedance of the line is not 50 ohms.

Using scikit-rf we can solve the characteristic impedance with the following code:

coefs = cal_trl.coefs
r = np.sqrt(coefs['forward reflection tracking'])
s1 = np.array([[coefs['forward directivity'],r],
        [r, coefs['forward source match']]]).transpose()
t = skrf.s2t(s1)
g = np.sqrt( (t[:,0,1] + t[:,1,0])**2/(4 + (t[:,0,1] + t[:,1,0])**2))
z = 50*(1+g)/(1-g)

t11 = (t[:,0,0] - 1/np.sqrt(1-g**2))*2/(50*np.sqrt(z/50.))
t22 = (t[:,1,1] - 1/np.sqrt(1-g**2))*2/(50*np.sqrt(z/50.))
xpad_est = (-1/t11 + 1/t22)/2

#Estimated pad capacitance
cpad_est = -1/(2*np.pi*f_ghz*1e9*xpad_est.imag)

#Plot the characteristic impedance
plt.figure()
plt.title('Z0 from error terms')
plt.plot(freqs, z)

Characteristic impedance solved from the error terms.

The method is only going to be accurate at low frequencies and in the above plot we can see that the estimated characteristic impedance of the lines is around 57 ohms. Accuracy is not very good and issue with low frequency measurements is that characteristic impedance increases as the frequency decreases. Reason for the increase can be found from the lumped element model characteristic impedance definition:

$$Z_0 = \sqrt{\frac{R + j \omega L}{G + j \omega C}}$$

As $\omega \rightarrow 0$, $Z_0 = \sqrt{R/G}$. $G$ is usually much smaller than $R$ and $Z_0$ approaches a large value. At high enough frequencies $Z_0 \approx \sqrt{L/C}$, which is constant.

Better estimate for the characteristic impedance can be obtained by solving for the capacitance per unit length and using the solved propagation constant from the TRL calibration to estimate the characteristic impedance. This assumes that $G \approx 0$, which should be true when substrate is not conductive.

c = np.real(-1j*cal_trl.gamma/(2*np.pi*freqs*z))

plt.figure()
plt.title('C0 from error terms')
plt.ylabel('Capacitance [F/m]')
plt.xlabel('Frequency [Hz]')
plt.plot(freqs, c)

Solved capacitance per unit length.

At low frequencies the capacitance per unit length is about 99 pF/m, but the obtained value is not very accurate because accuracy of the calibration is poor at low frequencies.

Assuming that the capacitance per unit length doesn't vary as a function of frequency, we can use the capacitance solved at low frequencies for solving the characteristic impedance over the whole frequency range. This is usually good approximation to make as long as the relative permittivity of the substrate doesn't vary much as a function of frequency.

z0 = cal_trl.gamma/(1j*2*np.pi*freqs*99e-12)

plt.figure()
plt.title('Z0 from C0 and $\gamma$')
plt.ylabel('Z0 [$\Omega$]')
plt.xlabel('Frequency [Hz]')
plt.plot(freqs, z0)

Characteristic impedance from C0 and propagation constant.

The trace is quite noisy and the resonance around 4.2 GHz in the line affects the propagation constant solution causing also the characteristic impedance to be solved incorrectly, but below 4 GHz the solution should be correct. At very low frequencies it can be seen that the characteristic impedance rises as is expected and after 1 GHz it is practically constant. From the plot characteristic impedance of the lines can be estimated to be about 56.7 Ω.

Second method

The previous method assumed that the SMA connector was well matched. A better method that doesn't assume can be used if line there is a terminated line on the board.

At low frequencies parasitics of the termination can be assumed to be low and impedance of the termination is the same as its DC resistance that can be measured very accurately with a multimeter. When the termination is measured with a VNA the expected reflection coefficient is:

$$\Gamma = \frac{R_{\text{load}} - Z_0}{R_{\text{load}} + Z_0}$$

This equation can be solved for $Z_0$, but it is again better to instead solve for capacitance per unit length because $Z_0$ is not constant at low frequencies.

#Calibrated termination
plt.figure()
cal_trl.apply_cal(trl_load).plot_s_db(n=0,m=0)

#Solve for Z0
r_load = 50.2 #Measure DC resistance of the termination
r = cal_trl.apply_cal(trl_load).s11.s.flatten()
z0 = r_load*(1-r)/(1+r)

plt.figure()
plt.title('Z0 from termination')
plt.xlabel('Frequency [Hz]')
plt.plot(f_ghz, np.real(z0))

#Solve for C0
c = np.real(cal_trl.gamma.imag/(2*np.pi*freqs*r_load)*((1+r)/(1-r)))

plt.figure()
plt.title('C0 from termination')
plt.xlabel('Frequency [Hz]')
plt.plot(freqs, c)

Measured S11 of the termination

Above are the TRL calibrated S-parameters of the termination. At low frequencies the S11 should be very low if $Z_0=R_{\text{load}}$, but the measured S11 is only -22 dB.

Solved Z0 using termination.

Solved capacitance using termination.

Solved Z0 seems to be around 57 Ω agreeing with the first method. Solved capacitance per unit length is about 98.8 pF/m, when previous method gave 99 pF/m. Now that we have gotten the same characteristic impedance using two methods we should be pretty confident in the result.

Renormalized TRL calibration

Finally the reference impedance of the TRL calibration be renormalized to 50 ohms by giving the capacitance per unit length to the calibration routine:

cal_trl = skrf.NISTMultilineTRL(
        measured = [trl_thru, trl_open, trl_line],
        Grefls = [1], #Estimate of the reflection coefficient
        er_est = 3, #Estimated effective permittivity
        l = [0, 13e-3], #Line lengths
        gamma_root_choice = 'real', #Assumes that lines are lossy
        switch_terms = switch_terms,
        isolation = ll,
        c0 = 98.8e-12,
        z0_ref = 50 #New reference impedance
        )

#Plot the smoothed characteristic impedance
#http://scipy.github.io/old-wiki/pages/Cookbook/SavitzkyGolay

plt.figure()
plt.title('Z0')
plt.ylabel('Z0 [$\Omega$]')
plt.xlabel('Frequency [Hz]')
plt.plot(f_ghz[1:], savitzky_golay(np.real(cal_trl.z0[1:]), 31, 2))

Characteristic impedance of the transmission lines. Smoothed using Savitzky Golay filter.

The resonance at 4.2 GHz gives incorrect results around that frequency, but the characteristic impedance can be expected to be constant at high frequencies. Reading from the plot the characteristic impedance seems to be around 56.7 Ω.

The line was supposed to be 50 ohms, but characteristic impedance seems to be over 10% bigger than that, so where's the problems?

Photo of the line with calibers for scale.

The first thing to check is that the manufactured dimensions of the line match the designed dimensions. In the picture is the microstrip line with calibers set to 1.00 mm for scale. In the image distance between the caliber jaws is 118 pixels, while line is 32 pixels wide. Converting this to mm gives line width of about 0.27 mm. The designed width was 0.34 mm so the manufactured line is thinner, which raises the characteristic impedance. Inputting the measured width to microstrip characteristic impedance calculator with nominal 35 µm trace thickness, 170 µm substrate height and substrate dielectric constant of 3.66 give characteristic impedance of 57.0 ohms.

The observed increase in the characteristic impedance can be fully explained by overetching of the lines. Overetching is about 35 µm, which is not bad considering the price of the PCBs. I have seen bigger overetching on much more expensive PCBs.

Termination S11.

Above is S11 of the termination with renormalized calibration. Now the low frequency reflection coefficient is small as expected. At high frequencies the reflection coefficient is not so good, but this is an issue with the termination and not measurement.

SMA connector S-parameters.

Plotting the solved SMA connector S-parameters from the error terms now gives the true 50 ohm normalized S-parameters. This time the connector matching looks much better. S11 and S22 are below -25 dB up to 4 GHz.

SMA connector S21.

Loss of the SMA connector is also very small.

Capacitor S-parameters.

Capacitor S-parameters don't look that different from before.

Capacitor S21.

At self-resonance frequency S21 is about 0.025 dB, when previously it was 0.022 dB. This gives ESR of 0.29 Ω, when without renormalizing it was estimated to be 0.26 Ω. Error is not very big in this case.

Part number of this capacitor is GRM155R71H102KA01J and Murata makes its S-parameter measurements available on their website.

Capacitor S-parameters from manufacturer.

My measurements include the PCB pads which cause some extra capacitance at high frequencies, but S-parameters measured by the manufacturer look very similar to what I measured. The manufacturer has measured the ESR to be 0.277 Ω which agrees really well with my measurement of 0.29 Ω.

Conclusion

Even though my VNA is much less accurate than commercial VNAs it is accurate enough for many useful measurements. I tried the same measurement also with the first version of the VNA and due to the much worse isolation the results were unusable.

The board had unfortunate resonance at 4.2 GHz, which I think comes from the poor grounding of the multiple ground planes. I think I'll need to order a new PCB with better grounding.

Improved homemade VNA

2017-03-13T00:00:00+02:00

Introduction

Last year I made a simple vector network analyzer for measuring S-parameters of microwave circuits that I'm making at home. Budget was very small and it was mostly a proof of concept for a low cost homemade VNA.

If you don't know what a vector network analyzer is I recommend that you read the previous post first, but in short it is a test device that can be used to measure magnitude and phase of transmitted and reflected power of a circuit. For example amount of power reflected back from antenna should be low at its working frequency.

While it worked and I could use it to measure one and two-port S-parameters measurement accuracy was not very good. One port measurements worked reasonably well but the biggest problem with two port measurement accuracy was leakage between the test ports. To even calibrate the instrument I had to use an exotic 16-term calibration that can compensate for different leakage paths between the receiver channels.

Lack of isolation between the ports was the biggest issue, but there were also many other smaller issues:

Receiver noise figure was very high since there wasn't any amplification before the mixer. Increased noise figure resulted in noisy measurement and reduced dynamic range.
Linearity of the receiver was not very good. This was partly caused by the bad choice of IF amplifier and partly because I used a balanced mixer without a balun. Mixer is recommended to be driven with differential input, but wideband baluns were too expensive. Driving the mixer with other input terminated was possible but linearity, conversion gain and noise figure suffered.
Directional couplers were integrated on the PCB and to save PCB area I made them as small as possible. At low frequencies coupling was very low and the signal to noise ratio at the receiver was not very good. At high frequencies directivity and matching of the couplers started to worsen.
In theory even if the matching, directivity or leakage were high they can be corrected by the calibration. In reality there is some amount of drift and noise in the instrument that causes the vector error correction to not be exact and some amount of error shows up in the results. There was enough drift, non-linearity and noise that there were significant errors in the measurement results even after the calibration.
Microcontroller was not fast enough to do any signal processing and all the signal processing needed to be done on the PC. This required transferring raw ADC values through the USB connection to the PC for processing. While the PC should be fast enough to process the samples without delaying the next measurement, in practice my code was written in Python which just wasn't fast enough to do all the signal processing without delaying the measurement. Microcontroller was also busy with reading the ADC and didn't have time to do anything else at the same time.

In total there were enough room for improvement that I wasn't be happy with the board and decided to make an improved version that tried to fix the problem points as well as I could while still keeping to cost low.

Single receiver VNA

Block diagram of the previous VNA version.

Above is the block diagram of the previous version of VNA. Commercial VNAs use four separate receivers with their own mixers and ADCs to maximize the isolation between the receiver channels and improve the measurements speed. I would also like to use the four receivers, but the reality is that multiplying the receiver cost by four is too much for my budget.

The isolation between the receiver channels can be improved by improving the isolation of the receiver SP4T switch. On my previous VNA I used a single PE42441 SP4T switch. It was very cheap, but the isolation is not good enough for VNA use. Commercial VNAs have isolation at least more than 100 dB between the receivers, but this switch has only 40 dB isolation at 6 GHz.

VNA should much higher isolation than the isolation of the component being tested and for example the isolation of the receiver switch couldn't be measured on the previous version of my VNA since leakage between the receiver channels is the same order as signal passing through the switch being measured. This is a general issue with test equipment: Its performance should be better than device being measured.

In addition to the receiver SP4T switch, port switch also had a single SP2T switch that didn't have good enough isolation. Source switch was PE42423, which is marketed as having an exceptional isolation of 43 dB at 6 GHz. While it is a very good isolation for a single SP2T switch it is not enough for VNA usage.

Achieving a isolation of more than 100 dB on a single PCB is hard and that is why professional RF test equipment have each system shielded from each other. If several blocks are made on the same PCB a milled aluminium case is placed on top of the PCB that isolated the blocks from each other and the environment. Aluminium block can also serve as a heat sink and reduce the temperature drift of the instrument. However I can't afford any custom milled aluminium pieces and have to manage without them.

I did however put a shield around the receiver that can be attached using clips so that it can be removed if needed. Shielding source, switches, couplers, FPGA and power supply would have also been a good choice, but it would have required too much space on the PCB so I decided to leave them out.

Block diagram of new VNA.

Above is a block diagram of the new VNA design. It is very similar to the block diagram of the previous version presented above. Port and receiver switches are changed to multiple SP2T switches in series as a single switch can't provide the necessary isolation. A low noise amplifier is added before the mixer to reduce the noise figure of the receiver.

Balun is also added before the mixer to increase its performance. Mixer is designed to be used with a balun that converts the single-ended RF signal to differential, but a wideband balun was too expensive. Only Minicircuits sells a wideband enough balun. It costs 8 € a piece with minimum order of 20 pieces plus shipping costs. Ordering the baluns would have cost more than all the other components combined, so I decided to leave it out and accept the performance loss in the first version. However I found a third party seller that sells the same balun for little extra at low quantities. With balun input return loss, conversion gain, noise figure and linearity of the mixer are improved.

Even though the block diagram looks very similar, there are also other big changes:

Microcontroller is replaced by FPGA which can do the digital signal processing on the board reducing the computing power required from the PC. On-board processing is much faster and the measurement speed should increase as it isn't necessary to transfer all the ADC samples to PC anymore.
ADC was previously a 12-bit ADC integrated on the microcontroller that was sampled at 10 MHz. It is now replaced by a 14-bit external ADC that is sampled at 40 MHz. This should greatly increase the dynamic range of the receiver.
Directional couplers were integrated on the PCB in the previous version but now they are on separate PCBs. This allows experimenting with different couplers and improving them without replacing the whole VNA.
Receiver is shielded from the other components. To improve the isolation from source to receiver, receiver is heavily isolated from everything else. RF signals are routed on the internal layers of the PCB with top and bottom ground planes to shield the signals as much as possible.

Receiver components labeled.

Above is a picture of the finished receiver section with different components labeled. Shield requires lot of space on the board, but it didn't affect the final PCB size too much, because SMA connectors and power supply limit the minimum board size.

Design

Schematic

Schematic. Click for PDF.

Mostly due to addition of FPGA number of sheets in the schematic almost doubled from 8 in the first version to 15 in the new version. BOM has 522 components, but it also counts for example mounting holes, RF footprints and test points that are PCB features. There are also many empty footprints that are not meant to be populated just in case. For comparison the previous version had 342 components in the BOM.

FPGA

Simplified FPGA block diagram.

Most of the high level logic, such as calculating the S-parameters from receiver readings and deciding the frequency points in the sweep, are done on the PC. On-board FPGA is responsible for low level processing such as toggling the IO lines based on the commands from the PC and calculating the IQ values from the ADC samples.

Digital signal processing works in the same way as the first version. ADC samples are divided in two branches where they are multiplied by $\cos(2\pi f t)$ and $\sin(2\pi f t)$. Frequency of the digital LO is the same as the output of the mixer, 2 MHz in this case. This results in the signal being mixed down to DC. Next average of the samples is taken resulting in two numbers I and Q.

Alternate way of thinking the DSP is that multiplying by sin and cos and then taking averages is equal to one frequency bin of Fourier transform:

$$ X_k = \frac{1}{N}\sum_{n=0}^{N-1} x_n e^{-2\pi i k n/N} $$

This is the optimal way to measure amplitude and phase of a signal with known frequency affected by gaussian noise.

Directional couplers

Resistive bridge coupler schematic. R1 and R5 are termination resistances of source and load and are not on the board. Z is the unknown impedance being measured. Vc voltage varies depending on the Z.

The previous directional couplers were stripline coupled line couplers that had two closely placed lines on internal layer of the PCB. It did work quite well at about 2-4 GHz but at lower frequencies the lines were very short compared to the wavelength of the signal and coupling was very low. This caused the receiver input power to be very low at low frequencies leading to very noisy measurements. Above 4 GHz directivity of the couplers wasn't very good. Ideally the coupler measuring the reflected signal wouldn't couple any signal going from the source to the test port and only couple the signals returning from the device under test going towards the source. In practice directional couplers have finite directivity and some of the signal passing from source to DUT is also coupled to the receiver. This directivity error must be measured during the calibration and removed from the measurements. Subtraction of the directivity error isn't perfect and it is preferred if it is low enough so that potential errors between the measured and real directivity doesn't cause big error in the measurement result.

For the new directional couplers I decided to change the architecture to resistive bridge coupler as it can give very flat coupling over very wide bandwidth from kHz frequencies to over 10 GHz. As the name says it is based on resistors that don't have frequency dependence like coupled lines and the frequency response is only limited by parasitics. Commercial VNAs often have resistive bridge couplers to reach the kHz frequencies where transmission line based couplers aren't practical.

A resistive bridge is basically a variation of Wheatstone bridge. A coaxial balun is inserted to the bridge to allow connecting a single ended load. Normally the coaxial cable should be long compared to the signal wavelength, but lower frequency limit of the balun can be extended by adding ferrite beads around the coaxial cable. Ferrite beads attenuate the common mode signals at low frequencies and allow using a much shorted coaxial cable.

Resistor values are also modified a little compared to the normal Wheatstone bridge circuit, so that through loss is lower and coupling loss is higher. See this paper for a good overview on how this coupler architecture works.

Design of my coupler is based on this IEEE paper.

Directional coupler PCBs.

Short piece of coaxial cable for balun.

SMD resistors are soldered upside down to minimize parasitics.

At least in theory SMD resistor soldered upside down should have little bit lower parasitic inductance than when it's soldered the right way. The resistive element is on top side of the resistor and by mounting it upside down it is closer to the PCB ground plane lowering its inductance.

Two finished couplers with ferrite beads around the coaxial cable.

Measured S-parameters of the coupler.

In the above plots are measured S-parameters with a commercial VNA up to 10 GHz. Coupler was measured as a two port with third port terminated with a high quality termination from the VNA calibration kit.

S12 trace is the through path, S13 is the coupled path and S23 is the isolated direction. Directivity is S13 - S23 and it is better than 25 dB up to 5.5 GHz and about 15 dB after it. Matching is very good at low frequencies but starts to worsen as the frequency increases. Through loss is about 1.5 dB.

Measured S-parameters of the coupler. Logarithmic scale.

Low frequency performance can be more easily seen when the X-axis is changed to logarithmic. Ferrites on the coaxial balun extend the low frequency range and the coupler still has about 5 dB directivity at 300 kHz.

Overall I'm very happy with the performance of the coupler. Matching, directivity and flatness of the coupling are all much better than the coupled line coupler on the previous version of the VNA. Using these couplers should result in much more accurate measurements.

Soldering

Bare PCB.

PCB secured for solder paste stenciling.

Like the first version, PCB is from OSH Park. OSH Park offers 4-layer FR408 substrate PCB that has lower loss and better controlled dielectric constant at high frequencies. It seems to currently be the only cheap non-FR4 process and if you have read my other posts I have used it a lot.

Previously I have made the backside of the PCB first, but I have found that it makes applying the solder paste on the front side more difficult as the board won't sit straight on the table. This time I decided to do the front side with difficult components first and do the backside by hand later. Having a flat backside without components helped with securing the PCB and the stenciling result was better than the last time. Stainless steel stencil should also help with the solder paste application and should result in better defined edges of the deposits than polyimide stencils I have used before. Stencil is from OSH stencils.

Solder paste on stencil.

After spreading the paste.

Solder paste on BGA footprint.

Solder paste on RF source components.

Solder paste stenciling was very successful. Edges of the paste deposits are very well defined.

BGA placed on the solder paste. Ball pitch is 1 mm, which is very easy to position even by hand.

Xilinx FPGA comes in a 256 ball package with 1 mm ball pitch. It is very big pitch for a BGA package and makes it very easy to solder at home. There is also comfortable amount of room to route all the signals even on a low cost PCB like this.

Components placed on the paste.

PCB in the reflow oven.

I used the same old toaster oven for reflow that I have made all my other projects with. Green PCB on the back holds the temperature sensor.

Hello world!

I made a quick bitfile for FPGA that just blinks the LED and everything worked the first time.

Measurements

Receiver

ADC output waveform.

External 14-bit ADC makes a big difference to the receiver dynamic range compared to the previous 12-bit ADC integrated in the microcontroller. Mixer output frequency is programmable and is set to 2 MHz in the above plot. Exact frequency isn't important, but there are some limits for setting the frequency. At low frequencies there is a dithering signal and more noise and at high frequencies linearity of the IF amplifier and ADC isn't as good. At some point the anti-aliasing filter will also start to attenuate the signal. 2 MHz is a good compromise.

Sampling frequency of the ADC is 40 MHz. In theory it could be much lower without aliasing and high sample rate ADC costs more so why not use for example 10 MHz ADC instead? There are three reasons:

To simplify the clock distribution FPGA, PLLs and ADC use the same clock signal. 40 MHz is a good value for all of them. If different clock frequencies were used, clock dividers or PLLs would be need to be added. FPGA could use separate clock, but PLL reference clock and ADC sampling clock need to be synchronized.
High sampling speed allows using simpler anti-aliasing filter.
Sampling speed can be traded for accuracy. When two consecutive ADC samples are averaged dynamic range increases by 3 dB. Quadrupling the sampling speed and taking average of four samples increases dynamic range by 6 dB, which equals increase of one bit in the sample depth. Dynamic range of 40 MHz 14-bit ADC is equivalent to 10 MHz 15-bit ADC or 2.5 MHz 16-bit ADC.

FFT of 5000 ADC samples. Y-axis is dB full scale. Maximum non-clipping input sine wave would be 0 dB.

Above is an FFT of 5000 ADC samples which is the maximum I can store at the FPGA and transfer to the PC at the moment. USB is not fast enough to continuously stream the ADC samples. Noise floor is about -105 dBFs. 5000 samples corresponds to 8 kHz wide FFT bin and sampling time of 125 µs. Every doubling of the sampling time increases the dynamic range by 3 dB. With 10 ms sampling time (100 Hz IF bandwidth) dynamic range is 125 dB and 0.1 s (10 Hz IF bandwidth) gives a dynamic range of 135 dB.

For comparison the previous version had dynamic range of 90 dB with sampling time of 400us. Due to needing to transfer all the samples to PC this setting was about as fast 5 ms sampling time on the new version. Because of better ADC, receiver LNA and on-board processing the dynamic range increased by at least 30 dB for the same measurement speed.

One port S-parameters

Making accurate one port S-parameter measurements is much easier than two port measurements. Error model is much simpler and isolation isn't as big of a problem. One port measurement can be completely corrected with three parameter error network, while two port error network has at least nine parameters.

Homemade SMA calibration kit. Open, short and load.

Measured calibration kit S-parameters.

Previously I didn't have information about the true S-parameters of the calibration kit and had to make a guess that decreased the accuracy of the measured S-parameters.

I measured the S-parameters of the calibration kit with commercial VNA calibrated with a very accurate and expensive calibration kit. This basically transfers the calibration of the expensive kit to my homemade kit and allows me to make reasonable accurate measurements with the homemade kit.

Uncalibrated S-parameters of the calibration standards.

Above are the raw uncalibrated measurements of the calibration standards measured with my VNA. Load is measured to be -30 dB because of the limited directivity of the couplers. Ripple is caused by the variation in the source matching. Open and short are not centered at 0 dB, because of loss of the couplers. All these errors can be determined from the measurements and corrected.

Solved error terms.

Compared to the same measurement with the previous version error terms are now clearly much smaller. New couplers have better directivity and matching reducing the ripple in open and short measurements and improving the dynamic range of the load measurement.

Patch antenna

Picture of the patch antenna and simulated and measured S11 traces.

Above is a simple patch antenna designed to work at 5.8 GHz. "patch_cal" trace is the measured S11 and "patch_simulation" is the S11 from EM-simulator. Measured S11 agrees very well with the simulated one and the trace is very clean.

Zoom into patch antenna S11 trace.

Trace noise in the patch antenna S11 measurement is about 0.1 dB, which is probably caused by the variation of the leakage from source to receivers. Below 700 MHz performance is much better because isolation is much higher at low frequencies.

Horn antenna

6 GHz radar horn antenna compared to commercial VNA measurement.

Above is a S11 measurement ("horn_left_cal" trace) of my homemade horn antennas compared to a measurement made with a commercial VNA ("horn_left_ref" trace). Compared to the measurement with last version traces are now much closer. Most of the improvement is from measuring the calibration kit.

Other horn antenna.

The other horn antenna also agrees quite well.

Two port S-parameters

Resistive bridge couplers on port 1 (down). Stripline coupled line coupler on port 2 (up).

I didn't have enough of the new resistive bridge couplers for both ports. So for two port measurements I had to put coupled line coupler from the previous version on the second port. It reduces the accuracy, but at least it allows me to make measurements.

Previous version had such high leakage between the channels that I had to use a special 16-term calibration that also calibrates for all the possible leakage paths. This version has better isolation and I'm able to use the normal SOLT calibration with isolation calibration (Both ports terminated).

20 dB attenuator S-parameters.

Above are the measured S-parameters of 20 dB attenuator. I measured the same attenuator also with the old VNA and using the same 12-term calibration quality was pretty terrible. With 16-term calibration that includes additional leakage paths I managed to measure it. There's a clear difference in the S11 and S22 accuracy between the new and the old versions. Ripple in the traces is unphysical and they should be smooth.

20 dB attenuator S-parameters. S21, S12 detail.

Above is the same measurement zoomed to the S12 and S21 traces. Ripple increases as the frequency increases due to the leakage being bigger at high frequencies. At low frequencies there's also some difference between the S21 and S12 traces due to different couplers on different ports. Port 1 had the new resistive bridge couplers while port 2 had coupled line coupler that has very low coupling at low frequencies which decreases the measurement accuracy.

Resistive bridge coupler with ports labeled. Port 3 is terminated with load.

I made three bridge couplers, two are used on the port 1 so one is left to be measured. Above is a picture of the coupler with ports labeled. In the picture port 3 is terminated with load so that it can be measured with two port VNA. Port 1 to port 2 is the through path with low loss. Port 1 to port 3 is coupling path that has 16 dB loss. Port 2 to port 3 is the isolated path with low coupling.

Coupler port 1 to port 3, with port 2 terminated.

In the above picture are the two port S-parameters of the coupler measured with my 300 € VNA calibrated with 5 € homemade calibration kit ("coupler2_13_term_cal" traces) and with commercial 100 000€ VNA calibrated with 5 000€ calibration kit ("coupler2_13_ref" traces). While my measurements are much noisier the traces agree very closely.

Coupler port 2 to port 3, with port 1 terminated.

Port 2 to port 3 measurement also agrees well. If you compare these measurements to one presented before, you notice that the directivity is not as good. Reason is that these measurements have been made with very cheap termination that has higher reflection coefficient. In the directivity measurement the terminated port reflects some power and measured S21 is bigger than it would be with a perfect termination.

Isolation

Isolation performance of the VNA didn't turn out to be as good as I hoped. I knew before that I wouldn't get the best performance without very good shielding, but I wanted to avoid it as good shielding is too expensive. It seems that most of the leakage is radiative leakage from source to receiver, but there is also more leakage between the receiver channels than expected. I did try to find and fix some of the worst unintentional antennas.

Port 2 reference channel (RX2) measured with source on port 1. With and without 10 pF capacitor on amplifier shutdown trace.

Source amplifier has a shutdown pin that is connected to FPGA and routed on top layer of the PCB for a long distance. I placed a 100 ohm resistor near the amplifier pin to add some loss to the line. However it turns out that at about 5 GHz the shutdown pin trace is the biggest leakage source. After adding a 10 pF capacitor from the trace to ground leakage dropped by 20 dB at 5 GHz.

Amplifier shutdown trace, series resistor and the added capacitor. Skinny trace on the right is the shutdown trace. Source amplifier is the IC on bottom left.

Port 2 reference channel (RX2) measured with source on port 1. With and without hand over the coupler cables.

At about 700 MHz there is another peak in the leakage plot. This one seems to be caused by the external couplers. If I place my hand over both of the couplers leakage is attenuated by about 20 dB.

There are many more similar unintentional antennas and I can't fix all of them. I guess the only way to improve the isolation is to shield every subsystem and preferably even make them on different PCBs.

Stability

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On the above video you can see how waving my hand over the board affects the receiver readings. Source frequency is 6 GHz and it is connected to port 1 causing the high readings on the port 1 channels RX1 and A. Test cables are open so ideally RX2 and B channels shouldn't have any power entering them. However due to leakage some power is detected at RX2 and B channels. Moving my hand either raises or lowers the detected leakage based on whether the reflected signal from my hand is in or out of phase with the other leakage paths.

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S11 measurement is also affected by the isolation. The absolute effect is smaller because signals are bigger, but I can affect the S11 readings by about 0.01 dB from about 0.5 m away by moving my hand over the VNA. IF bandwidth was 100 Hz.

Trace noise is also visible in the plot at the beginning. It is about 0.002 dB which is quite good but due to the poor isolation trace noise in the measurements is much higher. With a good isolation trace noise would be about this level also on the measured S-parameters.

Conclusion

The new version of the VNA is much more accurate than the previous version. Receiver is very accurate and has good dynamic range, but like the last version isolation limits the performance. A metal case around the PCB would help with stability and should increase the measurement accuracy. With case, shields around the individual subcircuits and receiver on a separate PCB measurement accuracy should be much better.

All the design files are available at Github.

RF power detector and scalar network analyzer

2016-10-25T00:00:00+03:00

Finisihed power detector.

Introduction

Continuing with the self-made RF test equipment theme I decided to next make an RF power meter. Accuracy of the finished power detector should be good enough for calibrating the output power of my VNA and measuring the output power of my radars. I'll be happy with +- 1 dB accuracy and sometimes even a worse accuracy is useful in measuring if there is any signal at all. USB connection is nice to have so that I can connect the meter to computer and for example automatically measure power of the VNA over the whole frequency range without having to manually write down all the measurement results.

Schematic

Schematic. Click for PDF.

Power detector could be done simply with a diode followed by capacitor similar to peak detector circuit used at lower frequencies. Diode will rectify the RF signal and generates a DC voltage which is proportional to the RF power.

While it would be possible to design the detector using a discrete diode and matching circuit, it is much cheaper, easier and accurate to use integrated circuit already containing the necessary circuit, matching circuit and temperature compensation. Existing ICs are also very well characterized so hopefully I don't need to calibrate the power sensor myself.

Searching on Digikey brings up several power detector ICs with most suitable looking to be AD8319. It works from 1 MHz to 10 GHz, has good accuracy, dynamic range and temperature stability. Package is 8-pin SMD package that can fit on a 2 layer PCB. Using 2 layer PCB instead of 4 would halve the price of the PCB.

I chose to use LPC11U68 microcontroller to interface to the computer. It is very cheap, has USB, doesn't need external programmer and I'm already familiar with some of the other LPC family processors so the programming should be easy. It is available in 48-pin QFP package which also can be routed on 2 layer PCB.

Only a voltage regulator IC is needed to complete the design. Having had a good experience using LP5907 regulator in my VNA I decided to use the same regulator on this project. It has very good power supply rejection ratio and low noise for the price.

RF traces on PCB. SMA connector on right, matching components and input to power detector IC.

On a 4 layer board SMA connector needed a cutout under the signal pad because 50 ohm microstrip line is only 0.34 mm wide, while signal pad is 1.5 mm. Without the cutout, pad would work as very low impedance transmission line causing reflections. Cutout removes the closest ground under the pad raising its impedance. 2 layer board is so thick that the 50 ohm microstrip is about 3 mm thick and instead ground plane on the top side needs to be brought closer to the signal pad to decrease the impedance of the line.

3 mm microstrip line would be very wide and make it hard to interface with components. Changing microstrip to grounded CPW with 0.2mm ground gap can be used to reduce the line width to 1.5 mm. While it's still quite wide, it's easier to interface with components than 3 mm line.

Manufacturing

Bare PCB from OSH Park.

Manually dispensed solder paste on PCB.

Components added on top of solder paste.

I didn't feel like I needed a stencil on this simple board, so I dispensed the solder paste manually. I did have few short circuits on the microcontroller pins that I fixed manually, but otherwise it worked fine. Soldering was done on my reflow oven made from toaster oven.

Measurements

I don't have a reference power detector to measure the absolute accuracy of the detected power, but I can use my VNA to generate a low frequency signal and measure its voltage with oscilloscope and power with power detector. Power of the signal can be calculated from the oscilloscope voltage measurement and it should be more accurate than the power detector reading. Power detector reading can then be adjusted so that it shows the same power. This method only corrects the reading at one frequency, but datasheet of the power detector has calibration curves that show how the power changes as function of frequency. There's still issue with frequency dependent losses on the PCB, but those can be assumed to be small. As a result power detector should be sort of accurate.

Power detector has limited range of powers that it can measure accurately. I can use my VNA to also measure the linearity range of the power detector. VNA has PE43711 0 - 31.25 dB variable attenuator that controls the output signal power. Attenuator is much more linear than the power detector, so measuring the output power of the VNA with different attenuation settings should reveal how good the power detector linearity is.

VNA power sweep at 100 MHz measured with power detector. 20 dB attenuator was used at the detector input.

Power detector is connected to the output of the VNA with 20 dB fixed attenuator in between to limit the power to detector. I wrote a quick Python script to step the attenuator values and measure the power at the output of the VNA using power detector. At 100 MHz the linearity seems to be quite good. Since there is a 20 dB attenuator before the power detector, maximum output power of the VNA is about 13 dBm at this frequency.

At 1 GHz power output of the VNA drops a little bit and the linearity can be seen to drop a little bit below -40 dBm.

At 6 GHz the output power of the VNA drops further. Now the maximum output power is under 0 dBm. It could be raised few dBm by increasing the output power of the PLL, which was set to medium power setting for this measurement. Below -45 dBm reading starts to significantly deviate from linear.

Input matching

Input matching of the detector chip itself is very high impedance, so the matching suggested by the datasheet is 50 ohm resistor to ground before the detector input. I used the suggested matching on my PCB since I wanted it to have a good matching over wide bandwidth.

Input reflection coefficient of the power detector measured with my VNA.

While the matching at low frequencies is very good, at high frequencies it quickly becomes very poor. At 4.5 GHz matching is only -3.4 dB.

Block diagram of the input matching.

Cause of the poor matching at high frequencies is the TX line 2 before the power detector input. At low frequencies length of the transmission line is electrically short and looking from the SMA detector board looks like high impedance power detector in parallel with 50 ohm resistor, which is close to 50 ohms giving good matching. At high frequencies the transmission line isn't anymore electrically short and when it is 90 degrees long the high impedance of power detector looks like a very small resistance (Transmission line works as a quarter-wave transformer). When a short circuit is in parallel to the 50 ohm resistor, result is still a short circuit resulting in a poor matching.

At 6 GHz 90 degrees long grounded CPW transmission line is about 7 mm long. Trace from resistor to the detector input is about 4 mm long and there are also 1.6 mm tall vias from component ground pad to bottom ground of the PCB. Power detector also has some transmission line inside it from wirebonds inside the package and the total transmission line length is more than 90 degrees at high frequencies.

Simulation model and measurement of the input matching.

After fitting the second transmission line parameters to the measured results the simulated input matching agrees very close to the measured matching. Power detector was simulated as 1000 ohm resistance, which is correct at low frequencies. At high frequencies resistance is about 100 ohms which explains the slightly better measured results.

Layout of the RF input.

Looking at the PCB layout of the power detector there are few ways to modify it to improve the matching. Especially RF grounding of the power detector isn't very good. On 2 layer board vias are 1.6 mm tall, which is a long distance at high frequencies. One way to improve the grounding would be to connect top side grounds of the input transmission line to directly to the ground pad of the component. This way ground current doesn't have to go through vias. Although even with this change matching wouldn't still be that good at high frequencies. Input DC block capacitor could also be changed to 0201 package so that 50 ohm resistor can be mounted closer to the input.

Improved layout.

In above picture the grounding of the component is improved by connecting the top side ground to component ground pad (Both sides of the pin 1).

Scalar network analyzer

Scalar network analyzer block diagram.

Using two directional coupler, two power detectors and RF signal source a scalar network analyzer can be made. Two directional couplers are connected so that other measures output power of the signal source and other measures the reflected power from the device under test. Ratio of the reflected and transmitted power gives the reflection coefficient of the device being tested.

I don't really need a scalar network analyzer since I have a VNA that has much better accuracy. It is however a nice project and I have all the necessary parts to make it already, so why not?

Similarly to the VNA I made before it can be used to measure reflection coefficient of the device under test. Difference between vector and scalar network analyzer is that scalar network analyzer can only measure the magnitude of the reflection coefficient while vector network analyzer can also measure the phase of the reflected signal. Measured phase can be used to calibrate the instrument enabling it to measure with much higher accuracy, as the scalar network analyzer can't measure phase it can't be calibrated the same way VNA can be and as a result it isn't going to be as accurate.

Scalar network analyzer connection.

I have already made a double directional coupler board with the same directional coupler that was used in my VNA. VNA can be used as a signal source and of course the power detectors are the ones I have just made.

Load, open and short measured using scalar network analyzer.

Above are measured results of short, open and load. Ideally open and short would be straight lines at 0 dB and load would have very low reflection coefficient. Clearly this is not the case here and especially short and open aren't straight lines, but instead have high ripple on them.

Directivity of the directional coupler is about 20 dB, which means that transmitted power going through the directional coupler measuring the reflected power will couple to the power detector with level of 20 dB less than if it would be going the right way. This means that even if the DUT absorbs the signal perfectly without reflecting anything, reflected power is measured to be 20 dB below the transmitted power due to directivity error. This is exactly what is observed when measuring the load.

Ripple in short and open measurements is also caused by directivity error of the directional couplers. Some of the transmitted power from signal source is coupled to the power detector measuring the reflected power and some of the reflected power is measured by the power detector measuring the transmitted power. If the right way coupled and wrong way coupled signals are in phase they will add up and power detector measured bigger power than without the directivity error. If the phases are opposite, signals partially cancel and measured power is lower. As the phase of the reflected signal varies as a function of frequency it causes the observed ripple pattern on the plot.

Measured S-parameters of the coupler board from input to coupling port.

At low frequencies the open and short measurements are very noisy and load seems to have very poor matching. These are caused by the too low coupled power to the power detectors. Coupler board I'm using has low coupling at low frequencies and dynamic range of the power detectors isn't good enough to measure the low power and it shows the noise floor.

Ideal open and short have reflection coefficients of 1 and -1. All of the power is reflected and phase difference between them is 180 degrees. When average of short and open measurements is taken the directivity error is cancelled. As the standards have high reflection coefficient and they don't absorb any power, their averaged measurement measures the losses in the measurement system. Subtracting the average of open and short measurements from other measurements can then be used to correct for the losses in system. It will also correct for the mismatch in sensed power of the two power detectors.

Reflection tracking error calculated from the previous measurements by averaging open and short measurements.

Same measurement as above, but with reflection tracking corrected.

Even with the reflection tracking corrected, ripple on the traces doesn't go anywhere because directivity and matching errors remain uncorrected. Without measuring the phase of the signal they can't be corrected. Accurate measurements using scalar network analyzer require good directivity and good matching from all the components.

Measuring SMA dipole antenna

In order to have something to test the scalar network analyzer with I made a simple half-wave dipole antenna by soldering two wires on SMA connector. Target frequency is 2 GHz, which means that the length of the quarter-wave long wires should be about 37.5mm. Really the wires should be little shorter due to gap between the wires on connector increasing the antenna length by few mm. Thickness of the wires also causes some electric field to fringe also to the ends of the wires increasing their electrical length. It's expected that resonance frequency is little lower than 2 GHz due to these effects.

End-launch SMA connector from China. Not very high quality.

Wires are ordinary single-core copper wire.

Finished SMA dipole antenna.

Measured return loss of the SMA dipole.

Measuring the return loss with the scalar network analyzer connection described above gives the above plot of the return loss. While the quality of the measurements isn't very good it can be seen that there seems to be resonance little below 2 GHz as expected and also other resonance around 5.5 GHz.

SMA dipole measured with VNA.

For comparison above is the same SMA dipole measured with my VNA. Even though it has similar directional coupler used with the scalar network analyzer measurements, results are much better because of vector error correction allows correcting for the matching and directivity errors.

Conclusion

Power detectors seem to work as designed except that input matching isn't very good at high frequencies. Absolute accuracy is questionable as I don't have a reference to compare it to.

Scalar network analyzer can't really compare to vector network analyzer. It can be made for much cheaper though and could be good enough for measuring antennas for hobbyist use.

You can find the hardware drawing, firmware and PC software on GitHub.

Cheap homemade 30 MHz - 6 GHz vector network analyzer

2016-08-02T00:00:00+03:00

Introduction

Vector network analyzer (VNA) are used to measure scattering parameters of high frequency circuits. When frequency is high enough the reflections of the waves start to matter and distributed effects need to be taken into account. VNA can be used to analyze reflection and transmission coefficients of circuits at high frequencies.

For example ideally antenna would radiate all the energy it gets, but all antennas reflect some of the energy back to the source and only radiate energy at certain frequencies. With VNA amount of energy reflected as function of frequency can be measured. Amplifiers also reflect some energy from both input and output and have some amount of gain. All of which can be measured using VNA.

Unfortunately VNAs are often very expensive and way out of my budget. Newest cutting edge VNAs with very wide frequency band can have insanely high cost. For example starting price of Anritsu's 110 GHz VectorStart ME7838A VNA is $575,850. Even used VNAs for lower frequencies are often several thousand dollars. At ebay cheapest used 6 GHz two port VNAs seem to sell for about 2,000€, still way more than I'm willing to pay.

Since I can't afford even a used VNA I decided to make one myself with a budget of 200€, tenth of what they cost used and about 1/100 of what they cost new. Of course it isn't going to be as accurate as commercial VNAs, but I don't need that high accuracy and it's a good learning experience anyway.

Block diagram

General block diagram of VNA.

$$ S_{11} = \frac{\text{A}}{\text{RX1}} $$

$$ S_{21} = \frac{\text{B}}{\text{RX1}} $$

So how does VNA measure reflection and transmission of signals? Operating principle is simple, but implementation is more challenging. Theoretically VNA consists of signal source that is used to excite the device under test (DUT), two directional coupler per port that measure transmitted and reflected waves and detectors at the end of the couplers that can measure both amplitude and phase of the signals.

Signal source generates a test signal which is routed to one of the ports. Part of the signal is coupled by the receiver directional coupler and its phase and amplitude are measured. Rest of the signal goes out of the VNA port and into the device under test. Some of the signal is reflected back to the source port and it is measured by another directional coupler. Ratio of reflected power to transmitted power is used to calculate the reflection coefficient of the DUT.

Non-reflected part of the signal goes through the DUT and can either be attenuated or amplified after passing through the device. When the test signal comes out of the DUT, part of the signal is coupled by the directional coupler on the second port and its phase and amplitude are measured. Rest of the signal passes to the termination where it is absorbed. Transmission coefficient is calculated as ratio of received power to transmitter power.

When measurement is repeated with the source switch connected the other way, reflection and transmission coefficients of the DUT can be measured from the other direction.

However in practice measurement isn't so simple. Biggest difference is length of the transmission lines inside the VNA and cables connecting the DUT causing loss and affection the measured phase. At 6 GHz wavelength on PCB is about 3 cm. For the phase difference between receivers to negligible distances from source, couplers and DUT should be much smaller than that. Especially cables connecting the VNA to the DUT need to be much longer than that so that device can be connected. There is also losses on cables, couplers and transmission lines inside the VNA. Directional couplers aren't perfectly directional and they couple also some signal coming from the other direction. Source and load matching aren't going to be perfect and will also reflect some signal back. There are also reflections from the internal components of the VNA. All of the errors also have some frequency dependence.

Block diagram with some of the error sources drawn.

However situation isn't hopeless as all of the error terms can be solved from measurements of devices with known reflection and transmission coefficients. When error terms are known, real reflection and transmission coefficients can be solved from the measurements. Usually very accurately characterized short, open and load standards are measured on both ports and through line is used to calibrate the transmission from port to port.

Four receiver VNA

Block diagram of common two port, four receiver VNA. Most of the commercial VNAs work like this.

If you want to see a more detailed block diagram of VNA, take a look at for example PNA-X Service Manual N5242-90001. On page 119 there is a very detailed block diagram of the RF parts. Above is a simplified version of the diagram.

Source is implemented using a phase locked loop and often frequency multipliers are used to reach the higher frequencies. To keep the output power level constant as a function of frequency, output power after the output amplifier is measured and attenuator before the amplifier is adjusted until the sensed power is correct.

Power coupled into the directional couplers is high frequency and it needs to be mixed down before it can be detected. Super heterodyne receiver with one intermediate frequency is often used receiver architecture that avoids complications with mixing straight to the DC. In this case the signal exists only at one frequency and this allows setting the intermediate frequency very low, about few MHz, and doing the final mixing digitally. Digital mixing has advantage over analog implementation in that while no analog component can be perfect, digital mixing can be made as accurately as needed. Analog mixers add noise, phases of the LO signals of two mixers aren't perfectly equal, performance varies as a function of temperature and operating voltage and so on. None of these errors exist with digital mixing and measured result is much more accurate.

While this is a good architecture for making a VNA, it has a drawback of needing many expensive components. 30 MHz - 6 GHz mixer costs about 10€, high accuracy ADCs about 10 - 20 €, fast microcontroller, or better, FPGA is needed to interface to the ADCs, control switches, toggle other signals and communicate with computer. Just these components cost at least 100 € and many more components are still needed such as PLLs, oscillators, filters, PCBs, power converters and so on. Whole board would be way too expensive so something has to be removed to save money.

Single receiver VNA

Block diagram of my VNA.

Most radical way to simplify the block diagram is replacing the receivers with single receiver and SP4T switch. This removes three ADCs, mixers and filters while adding a single switch. Signal processing is also simplified since now we must only measure one ADC instead of four. This change does have some drawbacks. Firstly the SP4T switch isn't perfect and it will have some leakage between the receiver channels. In theory it can be calibrated out, but it will reduce dynamic range of the measurements. Secondly previously all of the four channels could be measured at the same time, but now only one channel can be measured at once. This increases the time required to measure a single frequency sweep by four times.

Local oscillator can also be simplified as harmonics and exact power level doesn't matter that much as long as it is withing the specifications of the mixer.

In practice leakage from the SP4T switch is going to be a problem with calibration. Normal VNAs use high quality components and crosstalk between the ports can be assumed to be non-existent. With this architecture unless care is taken to minimize the crosstalk (which would require increased cost), it can't be assumed to be zero. Normal calibration procedures are unable to correct for it and there will be errors in the final measurements. There are more complicated special calibration procedures that can correct the leakage, so calibrating is still possible.

Design

Directional coupler

Coupled line coupler. When wave is passed from port 1, most of it goes through to the port 2 and some of it will be coupled to the port 3. When wave is passed from port 2, most of it will again go through to port 1, but some of it will couple. This time the coupled wave will be absorbed by the termination resistor and ideally nothing is detected on port 3.

The heart of the VNA are the directional couplers. In theory they can be made simply with two lines side by side with small gap between them. When a high frequency wave passes through one of the lines some signal couples to the nearby line. The coupled wave also prefers to go in one direction and ideally nothing would go to the other direction, but in reality there is small signal also to the other direction. Ratio of how much power goes to right direction compared to the power going to the wrong direction is called directivity. A good coupler can have directivity of more than 30 dB (one thousandth of power going to the wrong direction).

Microstrip coupler from my radar.

How does the directivity affect the accuracy of VNA? If the directivity is 0 dB, then the coupler can't really be called directional anymore and transmitted and reflected waves can't be separated. Result is that VNA can't measure anything. If the directivity is poor, but above 0 dB, there is some error in the measurements. It can be calibrated out, but the dynamic range of receiver is limited and accuracy is reduced. So for accurate VNA we need to have as high directivity as possible.

Turns out that stripline coupler, where lines are on the internal layers of the PCB, can be made with higher directivity than microstrip coupler where lines are on the top side of the PCB. I don't really know the exact reason myself, it has something to do with that on microstrip one side is PCB with high relative permittivity and other side is air with lower permittivity. Stripline on the other hand is embedded inside PCB and so it has same material on both sides.

3D simulation model of two stripline directional couplers.

Simulated coupling in forward (S31) and reverse (S41) directions. S-parameters are plotted with scikit-rf python package.

Simulated directivity is 20 dB at low frequencies and 30 dB at high frequencies. Coupling decreases very rapidly at lower frequencies due to coupling lines being electrically very short compared to wavelength. Coupling at low frequencies can be improved by making a multi-stage coupler. I decided to not make one, because it would have required more PCB area and even single stage couplers are pretty big. As a result of it dynamic range at low frequencies is going to be poor. I'm more interested at high frequencies so reduced accuracy at lower frequecies doesn't matter too much.

There is still a potential problem with making a connection from microstrip trace on the top side to internal layer of the PCB. A via is needed, but does it work with low enough reflections at these frequencies?

3D simulation model of via.

I made a simulation of a via structure with one signal via and two ground vias close to it. It's important to add ground vias close to the signal via so that ground current can also change layers without needing to go too far.

Simulated return loss of the vias. Insertion loss is about 0.4 dB.

According to the simulations there doesn't seem to be any problems with this kind of via connection and return loss is very good. I even simulated it up to 16 GHz and according to the simulation it still works well at that frequency.

Source and local oscillator

PLL block diagram.

To accurately generate frequencies at GHz range a phase locked loop is needed. It can generate accurate signals using a feedback loop that compares output frequency of voltage controlled oscillator (VCO) divided by N to stable low frequency reference clock. Feedback loop tries to make these frequencies equal by adjusting the tuning voltage of the VCO. Result is that output frequency of the VCO is N times the reference clock frequency. By cleverly changing the divider value fractional division values can be realized.

Problem with wideband signal generation using PLL is that good quality voltage controlled oscillators are usually not very wideband. To generate signals over wide bandwidth there are several different options:

Frequency multipliers and dividers can be used to extend frequency range. Disadvantage of this approach is that they both generate high number of harmonics so filtering is needed.
Two PLL outputs can be mixed together to generate sum and difference frequencies. This also generates harmonics and needs a second PLL and mixer.
Multiple switched VCOs can be used. This requires logic for choosing a correct VCO and of course many VCOs are needed.

Luckily this problem has already been solved and there are several commercial PLL chips with integrated VCO bank and output frequency dividers. Some suitable ones are ADF4355 which can generate output frequencies from 54 MHz to 6.8 GHz and MAX2871 which can generate frequencies from 23.5 MHz to 6.0 GHz.

MAX2871 is a cheaper choice and it has a suitable frequency range, so I choose to use that. It has multiple VCOs and frequency dividers. Especially at lower frequencies frequency dividers can generate high harmonics and some filtering is needed to clean the signal. Because frequency band is so wide multiple filters are needed to cover it all without passing harmonics. I decided to use four filters working at 0 - 1.1 GHz, 1.1 - 2.1 GHz, 2.1 - 4.2 GHz and 4.2 - 6.0 GHz. More would be better especially at lower frequencies, but they would soon become too expensive compared to the advantage of having them. Four is a good choice from cost perspective, since RF switches with more than four poles are often more expensive than switches with less poles as there are less use for such switches. Connecting multiple switches in series is possible, but would need more PCB area.

More detailed block diagram of the source.

After the filters there is power leveling circuits consisting of variable attenuator, RF amplifier and power detector.

Variable attenuator is PE43711 that can be configured to have attenuation from 0 dB to 31.75 dB in steps of 0.25 dB.

RF amplifier needs to be very wideband, I chose to use TRF37A75 RF amplifier. It's a cheap 40 to 6000 MHz amplifier with 12 dB gain. Gain is very stable as function of frequency, it varies only about 3 dB over the whole frequency range. Output matching however could be better as it is only -7 dB at 6.0 GHz and reflections from the amplifier output will cause some errors in measurements. Now that I think it would have been a good idea to add some places for matching components so that matching could be improved afterwards, but it's too late for that now.

At the amplifier output there is a power detector connected using a 100 ohm resistor. The resistor works as a -10 dB coupler and capacitor is used for DC blocking.

Microcontroller is used as a part of the feedback loop. It could be done using operational amplifier based circuit, but it can't be used in this case. Power level of the source must remain constant during the measurement of different receiver channels or else there will be uncorrectable errors in the measurements.

PLL, filters and power leveling circuits on PCB. PLL has its own voltage regulator to reduce interferences. Big component under the detector text is actually ADC. Detector is the small 1.2 x 0.8 mm black box right of it.

Above is a picture of the source components on PCB. Especially around the amplifier area the components couldn't be placed more closely together. I even placed some DC blocking capacitors at 45 degree angle so that I could save few mm of space. I decided to add power leveling only after routing the rest of the PCB so space got little tight.

Local oscillator uses another MAX2871 chip to generate signal for the receiver mixer. Filtering this signal isn't necessary as harmonics don't degrade performance of the mixer. Power leveling isn't needed either as long as the power level stays within correct range. For accurate frequency generation it's important to use same reference clock for both source and LO. ADC sampling clock should also be derived from the same reference for the best accuracy. If they were to use different references, they could drift relative to each other. Using same reference means that even if the reference drifts, it will cancel out after sampling as all the frequencies drift the same amount.

Receiver

Receiver consists of SP4T switch, mixer, local oscillator, anti-aliasing filter and ADC.

Switch causes crosstalk between the channels reducing the accuracy of measurements. A very high isolation switch would be ideal for the best performance. Low loss is also welcome as high loss reduces the dynamic range, but high isolation is more important. Switch also needs to be absorptive instead of reflective on non-switched ports and of course work from 30 MHz to 6 GHz.

It would also be possible to use three SP2T switches and it would probably give better isolation. However single SP4T switch is simpler and optimizing performance isn't that critical. It's better to keep design simple at this point and optimize performance in next revisions.

I chose to use Peregrine PE42441 SP4T switch that has about 40 dB isolation. It does affect the accuracy, but hopefully not too much. Commercial VNAs have often very high >100 dB isolation between the ports, so this is very poor compared to them.

To my knowledge there is only one possible affordable mixer that can be used over the whole frequency range. It is the same ADL5801 mixer that I used on my radar.

Recommended mixer input connection.

Mixer has a balanced input and datasheet recommends using a balun to convert single-ended signal to differential signal for mixer input. Issue is that most of the baluns are narrowband, while this application needs a balun capable of operating over the whole frequency range from 30 MHz to 6 GHz. There is one balun from MiniCircuits that is capable of operating over the whole frequency range, but it costs 7€ a piece and I would need to order it directly from MiniCircuits.

Other option is to leave the balun out and drive the mixer single endedly. Other unused output is connected to ground through a capacitor. Since single ended input impedance of mixer is 25 ohms and the system impedance is 50 ohms, return loss of the mixer is going to worsen. Conversion gain and linearity will also suffer. It does however save 7€ (+shipping) and PCB area so it seems worth it.

IF filter.

LO frequency is set to 2 MHz below (or above, doesn't matter) source frequency. This gives a 2 MHz IF signal which is easy to sample and filter. On my radar filter could have been more aggressive and this time I added some optional filtering components that can be added if needed. Differential amplifier buffers the signal for ADC and slightly amplifies it. Final RC filter before ADC further attenuates high frequencies above sampling frequency to avoid aliasing.

DITHER signal is a noise signal that can be added to ADC input. Why add deliberately noise to the signal? Consider the case where signal to be measured is so small that peak-to-peak value is less than one ADC least significant bit. Then the ADC might only output constant value and nothing is detected. If a noise signal is added then some changes are always seen at the ADC output. This time the signal to be measured can affect the output value of ADC. If noise and signal have different frequencies then the noise signal can be filtered out. Since signal affected some of the output values it can be detected after filtering. So by adding noise dynamic range of the ADC was increased.

Find out more at this Analog devices article.

Good idea, but turns out that due to leakage between the channels there is always enough signal to be detected so it isn't needed.

Digital logic

Microcontroller (or FPGA) is needed on board to handle communication with computer and control all the devices. Since only one ADC is needed with the switched receivers I decided to save money and look for a microcontroller with integrated ADC.

Most suitable one I could find was NXP LPC4370. It has one ARM-Cortex M4 core and two Cortex-M0 cores, high speed (480 Mb/s) USB support and 80 MHz 12-bit ADC. Maximum clock frequency is 204 MHz, so it should be fast enough.

This part has the fastest integrated ADC that I have seen on any microcontroller. External ADCs with same clock rate and bit depth cost more than this whole microcontroller, so the cost savings are considerable. It's available in hobbyist unfriendly 100 and 256 ball BGA packages.

Voltage regulation

Block diagram of power supplies.

For high accuracy measurements it's important that there is no noise on the power supply that can make its way into the signal path. For my radar I made a mistake of using switching mode power supply for analog parts and ADC. While the noise was not very high, it was still detectable.

This time I decided to pay extra attention into the power supply design to minimize interferences. Still I didn't want to go too far, since high quality components can be expensive. For example shielding the RF parts would be helpful, but would cost too much.

Switching mode power supplies.

Power consumption of the board is about 3 W. Power consumption limit from USB bus is 0.5 W, so external supply is needed. 12 V is common AC adapter output voltage so I chose to use that as input voltage. There is some filtering right after the DC plug after which power goes to two L7980 switching mode power converters. Special feature of L7980 regulator is that switching frequencies of two different regulators can be synchronized by connecting two pins on the regulators together. Switching frequencies will synchronize in such a way that phase difference between the regulators is 180°. This results in lower input ripple as current draw from the input filtering capacitors is spaced apart. Having synchronized switching frequency is useful as there is noise only at one frequency on both 5V and 3.3 V rails.

If the frequencies wouldn't be synchronized mixing products of the different switching frequencies could be created. One path which this can happen is that if the power inductors are placed close to each other magnetic fields on the inductors can couple and switching noise is injected between them causing sum and difference terms of the switching frequencies to be detected at outputs of both of the regulators. Another path that switching noise can travel is through the shared input. As regulator switches it draws current and input voltage decreases a little bit. Because regulators share input voltage, noise is injected to output of the other regulator.

Care must also be taken when connecting a linear regulator after a switching regulator. Goal of this connection is usually to have good efficiency of the switching regulator and low noise of the linear regulator. Noise reduction can be much less than thought if power supply rejection rate (PSRR) of linear regulator isn't high enough at the switching frequency.

For example if we place MCP1700 3.3 V linear regulator after switching power supply that has a switching frequency of 100 kHz we will find that adding the linear regulator had barely any effect. Switching noise after the regulator is same as before it.

If we replace the linear regulator with LP5907 the switching noise after the linear regulator is gone. What's the difference between these two linear regulators?

PSRR of MCP1700.

PSRR of LP5907.

Looking at the power supply rejection rate plots on the datasheets of the devices we find that at 100 kHz MCP1700 has PSRR of about 0 dB. All the noise at this frequency just passes through. LP5907 has PSRR of -60 dB. For example a very large 0.1 V noise at the input would only be 100 µV at the regulator output.

MCP1700 does still have use cases. It is much cheaper and would be a good choice for powering digital systems where noise doesn't matter that much.

Schematic and layout

Schematic. Click for PDF.

Layout in KiCad.

PCB was designed with KiCad. New push-and-shove router is really helpful when routing a tight board like this.

This PCB is a personal record in saving PCB area. Size of the PCB is 52 mm x 57 mm and it has over 300 components mounted on both sides. It could have been made even smaller if it wasn't for the big directional couplers. Stripline construction requires that layers above and below it are left empty wasting a lot of space.

Soldering

Fresh PCBs. Manufactured by OSH Park.

First I soldered the passive components on the backside.

Stencil on the top side. Stencil is made by OSH stencils

Solder paste spread on PCB.

Components placed by hand.

After few minutes in oven components have been soldered.

Connecting power for the first time.

On first power up everything seemed to work fine. Although I found out that I had made a mistake in switching regulator compensation network design and both supplies had about 0.1 V switching noise riding on them. After recalculating and correcting the component values everything seemed to work fine. I could program the microcontroller, turn on the PLLs and see the correct looking IF signal with oscilloscope on the mixer output. It was working fine for few days, but suddenly though I couldn't communicate with the microcontroller anymore. I suspected an issue with soldering and I tried to reball the BGA and resolder it but it didn't help. I could communicate with the microcontroller again, but it would get hot and randomly hang when communicating through USB. I didn't find any mistakes on the layout. I also tried to remove and reball BGA on evaluation board of the same microcontroller and it started to have similar symptoms so I was pretty sure that there was something wrong with my soldering. Or maybe with the Chinese BGA balls I was using?

Unfortunately I didn't manage to get the BGA resoldered correctly and after few tries the solder mask of the BGA footprint was looking pretty damaged from desolderings.

Ruined PCB after removing the components.

So after letting the board be for few months I managed to find motivation to make another one. I desoldered the most expensive components and made a new board. This time I managed messed up soldering of the LO PLL package. I had broken my soldering iron while desoldering some of the components earlier and using my old unregulated iron I managed to lift data input pad of the LO PLL while cleaning the solder from the pads. I managed to solder a 0.1 mm diameter jump wire to QFN pad and the board could still be used.

Jump wire soldered on the side of QFN.

Microcontroller still heated up more than seemed normal. It wouldn't run stable at full operating frequency, but after reducing the frequency from 204 MHz to 108 MHz it seemed to be working, although still running hot. I still couldn't find any issues on the layout though so maybe there is still some issues with soldering?

Signal processing

Firmware is based on the HackRF and AirSpy firmwares. Thanks to these open source software already implementing many of the features I needed, firmware development was much easier than if I would have neede to start from scratch.

In short, the sampling part of the firmware works by first setting the source and LO frequencies based on the commands from computer. RF outputs and amplifier are enabled, port switch, source filter and source attenuator are set to the correct values and receiver SP4T switch is set to the first channel.

Then computer sends a command to start sampling. DMA is configured to transfer 16k samples from ADC to memory and raise interrupt when done. As DMA moves samples in the background SP4T switch is switched so that every channel is sampled. When DMA complete interrupt is raised samples are sent to the computer. If more averaging is needed sampling is repeated and measurements are averaged.

Samples on computer.

Computer program gets the recorded samples that look like in the plot above. In this case two port measurement is made so all four channels are sampled (In one port measurement sampling two channels is enough). First measurement is the port 2 reference channel RX2. Second is port 1 reflection channel A. Third is port 2 reflection B and fourth is port 1 reference RX1.

In this measurement we can see that source is connected to port 2 as port 1 channels RX1 and A only show leakage, while there is big signal on port 2 channels RX2 and B.

FFT of the RX2 channel samples.

Taking FFT of the RX2 channel samples reveals that the signal quality is quite good. ADC on the microcontroller also seems to perform surprisingly well. Y-axis units are in decibels full-scale, input sine wave with maximum amplitude without saturation would have an amplitude of 0 dB.

Signal level is -12 dB and noise floor near it is around -90 dB. Some noise can be seen near DC and bigger spurs at 3.6 and 4.0 MHz. High frequency spikes are likely result of mixer non-linearities. 4.0 MHz seems to be second harmonic of the IF signal, but I'm not sure where the 3.6 MHz comes from.

FFT of the A channel samples.

Taking FFT of the A receiver samples reveals that some signal is detected even though on the plot amplitude looks very low. Measured signal level is -50 dB full-scale. This time signals at 3.6 and 4.0 MHz have disappeared which makes sense if their level as mixer products is dependent on the signal level. However at 2.6 MHz there is a small spur. It can be seen on the first FFT too, although signal leaks little over it making it hard to see. Noise floor is at about -90 dB.

From the FFT plots magnitude and phase of the IF signal could be extracted, but there is no need to calculate all of the frequency bins when just one is needed.

$k$th frequency bin of discrete Fourier transform of signal $x$ is defined as:

$$ X_k = \frac{1}{N}\sum_{n=0}^{N-1} x_n e^{-2\pi i k n/N} $$

, where $N$ is the length of the signal. We can use this definition to calculate coefficient of only one frequency bin. Time complexity is O(n) instead of O(n log(n)) of FFT, so in theory it should be faster.

Generated digital second LO I and Q signals. In this plot frequency is lower than 2 MHz to make the shape more clear.

Two sine waves are generated at the signal frequency with phase difference of 90 degrees. Multiplying slices of the signal with samples from one channel and same index slices of two sine waves and taking separately averages of the results gives real and complex part of the IQ sample. Taking slice also of the LO signal is important for correct phase measurement. Absolute phases of the signals will vary as there isn't a reference channel to compare phase. However it isn't needed because S-parameters are defined as ratios of the measurements and relative phases are repeatable.

Next the port switch is switched and receivers are measured with source connected to the other port. After getting the IQ samples from all of the channels S-parameters can be calculated as ratios of calculated IQ sample of different receivers:

$$ S_{11} = \frac{\text{A}^1}{\text{RX1}^1} $$

$$ S_{21} = \frac{\text{B}^1}{\text{RX1}^1} $$

$$ S_{12} = \frac{\text{A}^2}{\text{RX2}^2} $$

$$ S_{22} = \frac{\text{B}^2}{\text{RX2}^2} $$

Superscript marks the port source is connected to.

We aren't however done yet. If we plot the S-parameters now we see that they don't look like they are supposed to. Reason is that there are many error sources in the measurements. Some of which are:

Reflections from the components inside VNA and external cables.
Directivity error from directional couplers.
Leakage between the receiver channels.
Attenuation and length of the cables and VNA internals.

Measuring the S-parameters of open circuit gives the following plots.

Ideally open circuit should have reflection coefficient of 0 dB and phase of the reflection should be 0 degrees.

To get accurate measurements errors must be characterized and mathematically removed from the measurements.

One port calibration

Calibrating one port measurements is much easier than two port as there are not as many error sources. Only one of the ports will be used and receivers on the second port are not measured at all. Result of the measurement is reflection coefficient of the device under test.

We can model the one-port VNA as an ideal VNA in series with error adapter. $a_0$ and $b_0$ are the measured RX1 and A channels. Measured reflection coefficient can be calculated simply as $b_0/a_0$.

In the error adapter $e_{00}$ term is the directivity error of the directional couplers. $e_{11}$ includes errors from port matching and $e_{10}e_{01}$ term is tracking error. It models different frequency responses of the detectors, for example phase error from cables is corrected by this term. $\Gamma$ is the actual reflection coefficient of the device under test and what we want to measure.

For good overview of VNA calibration methods see this document and this page for more detailed explanations of the error terms.

Error adapter has three unknown terms so by measuring three known devices we can solve for the error terms. With the solved error terms we can solve for the actual reflection coefficient of the DUT.

The only problem is that three accurately known devices are needed. If the actual reflection coefficients are different from the ones used in calibration, there will be errors in the measurements.

Accurate calibration standards are really expensive as they require very high precision construction. At ebay professional calibration standards with SMA connectors sell for 300 € to 5000 €. Even the cheapest ones cost more than I have so far spent on this project.

Following the example of IN3OTD who made simple calibration standards, I decided to make calibration standard myself.

Homemade SMA calibration kit. Open, short, match and through standards.

I took three through hole SMA female connectors. Cut off legs from one to make open, one was filled with solder to make short and match was made by soldering two 0805 0.1% 100 ohm resistors in parallel to the last one. Through standard is needed for two port calibration and it is a regular SMA female-to-female adapter.

Measuring the calibration standards.

Measuring a horn antenna.

Uncalibrated responses of calibration standards and horn antenna.

In the above plot are the uncalibrated S-parameters of calibration standards and horn antenna. With little imagination it can be seen that horn antenna looks like open circuit at low frequencies and is well matched above 5 GHz. This plot also tells that internal errors are biggest between 4 and 5 GHz as the ripple there has largest magnitude.

Calibration is done using existing one port calibration routine in scikit-rf Python library.

Input return loss of horn antenna measured with this VNA compared to measurements from professional grade VNA.

Above is the input return loss of horn antenna after calibration. Now the trace is much cleaner compared to the uncalibrated one. On blue is the return loss measured with this VNA and on red is same antenna measured using professional grade VNA made by Agilent. Exact model I used is now obsolete, but similar one would cost about 15,000€ as new. My VNA is able to make this measurement quite accurately considering the price difference. There are small differences in the plots, likely because of my inaccurate calibration standards.

Return loss of the other horn antenna.

Other horn antenna measurement also agrees with the measurement made with Agilent's VNA.

Two port calibration

Two port calibration is much more difficult than one port calibration because there is also additionally problem with calibrating the leakage away. Most commonly used error model is 12-term error model where both ports have 6 error terms, but this error model doesn't model leakage paths between different receivers and thus it can't remove errors caused by the leakage from the measurements.

12 term error model. Source

12 term error adapter parameters. Same model is used for the other port. Source

Calibration standards needed for this model are open, short, match and through. Open, short and match are measured at both ports one at a time and one port calibration is performed on both of the ports. Through measurement is used to calibrate the transmission from port to port. In the model there is a $e_{30}$ term that models port to port leakage, this isn't however solved in the scikit-rf package I'm using to calibrate. It is often assumed to be zero as good VNAs have very high isolation between the ports.

Measuring 20 dB attenuator

20 dB attenuator connected for measurement. Female-to-female SMA adapter is used on the male connector to connect to SMA cables.

To test the accuracy of 12 term SOLT (short, open, load, through) calibration I measured a 20 dB attenuator.

According to the seller this attenuator should have attenuation of 20 dB +- 2% and return loss better than -17 dB. However it is a cheap Chinese one so who knows what it really looks like?

Above is the SOLT calibrated S-parameters of the attenuator. Matching seems to be very good and it seems to fulfill the -17 dB specification. At low frequencies measured attenuation is -19.5 dB which is just outside the promised 2% accuracy. Slight offset might be caused by inaccurate calibration standards. At low frequencies traces look okay, but at high frequencies there is weird ripple which is also seen in S11 and S22 measurements. I assume this is due to leakage which isn't corrected by this model.

16 term error model. Source

To get more accurate measurements, error model is needed that takes into account the leakage terms between all of the receivers. 16-Term error model is a complete error model for two port VNA. It includes all the possible paths the signal can travel. Using this model on well isolated VNA causes more harm than benefit due to increased numerical errors if the real values of the leakage paths are below the measurement capability.

I decided to use a calibration method called LMR16. Due to increased number of unknowns in 16-term error model more measurements are needed. This method needs three different calibration standards: Through, match and reflect. Reflect can be any reflecting standard, match is assumed to be perfect and through is assumed to be lossless and well matched. Five different measurements are needed to get enough equations to solve for the unknown error terms:

Through (Ports connected together with through standard)
Match-Match (Match on both ports)
Reflect-Reflect (Reflect on both ports)
Reflect-Match (Reflect on port 1, match on port 2)
Match-Reflect (Match on port 1, reflect on port 2)

LMR16 is a self-calibration procedure that can either determine the correct length of the through standard when reflect standard is given or the other way. This is convenient feature since I don't know the electrical length of the through, but short and open models are reasonable accurate according to the one port measurements.

20 dB attenuator S-parameters with LMR16 calibration.

Above is the plot of the same 20 dB attenuator measurement, but this time calibrated using LMR16 calibration. Most of the ripple on the S21 and S12 plots has disappeared. Doing a secondary calibration using 12-Term SOLT further slightly improves the response as LMR16 assumes match standard to be perfect and SOLT calibration corrects for the non ideal match.

Response looks like it should. Insertion loss is very stable as a function of frequency and both ports are well matched. Some ripple is seen on S11 and S22 traces that looks like it shouldn't exists. Measured reflections are similar level as leakage so maybe there is some residual error left. I'm not sure why it exists, but some possible reasons I can think of are: inaccurate calibration standards and components heating up during the measurements and their parameters changing.

Solved through length is equal to 41.1 ps delay corresponding to about 8.7 mm long coaxial cable assuming that through material is PTFE.

Measuring coupler

Coupler with SMA connectors.

To have something to measure I made a coupler board with SMA connectors. Coupler has four ports, but VNA only has two so I used SMA terminations on the two unused ports.

In above plot through path is measured with terminations on the coupled line outputs. SMA connector and coupler seem to be well matched. Return loss is better than -17 dB over the whole range.

Close-up to the insertion loss.

Insertion loss of the coupler is also reasonable. About -1.3 dB at 6 GHz. Measured trace is also decent quality compared to the S21 trace with 12-term calibration. There is about 0.1 dB peak-to-peak ripple on it.

Measured forward coupling.

Next measurement is coupling in the forward direction. VNA was connected to the two rightmost ports while other two were terminated. Coupling at low frequencies is very low as was simulated. Peak coupling is -13 dB, when -15 dB was the simulated value.

Measured reverse coupling.

Coupling in the reverse side however is higher than expected. It doesn't seem that the directivity is as good as simulated. Some of it is because termination on the through port causes reflections. It can be seen on the S11 that return loss is much higher than when through was measured indicating that termination isn't well matched. Better termination or mathematically compensating for it would be needed for more accurate measurement.

It is however possible that the directivity at high frequencies isn't as good as simulated when looking at the uncalibrated values. Amplitude ripple is highest between 4 and 5 GHz where directivity is low according to the measurements.

Conclusion

Looking at the uncalibrated values internal errors of the VNA seem to be quite big at higher frequencies. Sweet spot for minimum errors and good coupling seems to be around 2 - 3 GHz and at this range VNA gives the best accuracy. With correct calibration procedure the errors can be calibrated out and resulting measurement are quite high quality when cost of the board is considered. Performance seems to be good enough for non-professional use. Simple measurements such as antenna return loss measurements can be performed with high accuracy.

I'm not selling these, but if you are interested in making your own VNA or are just interested in looking at the design files all hardware, firmware and processing software is available at GitHub.

Heartbeat detection with radar

2016-04-05T00:00:00+03:00

Introduction

Frequency modulated constant wave (FMCW) radar return signal from target is a sine wave and its frequency depends on the distance to target. Phase of this signal is very sensitive on the distance to the target.

By analyzing phase variation of the radar return signal very small movements can be resolved. Movements less much smaller than wavelength of the radar can be resolved, but downside is that two different targets can't be resolved any better than radar normally can (tens of cm to meters).

If you aren't interested in the mathematics about how this works you can scroll down and watch videos instead.

Mathematics

Let $x(t)$ be the transmitted linearly increasing frequency sweep from $f_c -B/2$ to $f_c + B/2$ in $t_s$ seconds:

$$ x(t) = \cos(\phi(t)),\quad -t_s/2 \leq t \leq t_s/2 $$

$$ \phi(t) = 2\pi f_c t+\pi \frac{B}{t_s}t^2$$

$f_c$ is the sweep center frequency, $B$ is sweep bandwidth and $t_s$ is sweep length. Amplitude of the signal is not important in this analysis and is set to 1.

Transmitted signal travels at speed of light and reflects of the target at distance $r$ and is received after time $\tau = \frac{2r}{c}$, where $c$ is speed of light.

Received signal is mixed with a copy of the transmitted signal which results in difference and sum of frequencies of the signals. Sum term is too high frequency (about twice the carrier frequency) and is filtered out. Difference term is low frequency, usually few kHz, and contains the information about the target:

$$ f(t) = \cos(\phi(t) - \phi(t - \tau)) = \cos\left(2\pi\left(\frac{B\tau}{t_s}t - \frac{B \tau^2}{2t_s} + f_c\tau \right)\right) $$

First term with $t$ dependency is frequency of the signal and last two terms are phase. When Fourier transform is taken frequency of the signal can be found out giving the distance to the target. Resolution of radar as defined by minimum distance of two targets such that they are detected separately follows from the resolution of Fourier transform. Length of Fourier transform is same as sweep length $t_s$. Resolution of discrete Fourier transform is sampling frequency $f_s$ divided by number of samples $N$: $\Delta f = f_s/N$. Because the signal is $t_s$ long, there are $f_s t_s$ samples. Frequency resolution can be improved by increasing the sweep length, but increasing the sweep length also decreases the frequency from the target. Changes balance out exactly and range resolution is independent of the sweep length:

$$ \frac{B2\Delta r}{ct_s} = \Delta f = \frac{1}{t_s} \Rightarrow \Delta r = \frac{c}{2B} $$

The phase terms also contain information about distance to target. $\pi \frac{B \tau^2}{t_s}$ term is called residual video phase term and due to $\tau^2$ term is very small and can often be ignored. Second phase term on the other hand can be expanded as:

$$ f_c\tau = f_c \frac{2 r}{c} = \frac{2 r}{\lambda} $$

where $\lambda$ is the wavelength of the sweep center frequency. Changing the distance to the target by half wavelength is enough to wrap the phase around. Phase noise of the radar determines the resolution the phase can be determined, but usually it should be possible to detect phase within few degrees.

At 5.6 GHz wavelength is 54 mm and assuming that minimum of 1 degree change in phase can be detected it gives the minimum detectable movement of 75 µm.

One drawback of using phase is that while it can sense small changes in distance, it can't resolve closely spaced targets any closer than is possible by analyzing the frequency term since Fourier transform is needed to get the phase. This means that if two equally reflecting targets are moving in opposite directions close together, then their movements cancel each other and radar doesn't detect either of them.

Your browser does not support the video tag.

In video above I'm moving the antenna a short distance and in the upper right corner there are plotted raw signal from ADC and Fourier transform of the same signal. Phase of the signal changes very rapidly, but the frequency stays unchanged at this scale due to the limited resolution of the radar.

Breathing and heartbeat detection

Your browser does not support the video tag.

Above is a short video of me sitting still facing the radar. First I'm breathing normally and then I hold my breath for short time.

Radar sends sweeps with linearly increasing frequency at 1 kHz repetition frequency. For every sweep the sampled signal is Fourier transformed so that returns from targets at different distances can be separated. Then phase of one of the FFT bins at distance where I'm sitting at is saved. Same processing is done for all of the sweeps and unwrapped phases are plotted to give the plot on the video.

Full unwrapped phase from the recorded data.

Above is the image of the measured phase. At the beginning where I'm walking phase wraps around multiple times and the breathing signal can't be seen at this scale.

Zoomed in to breathing

Above is zoomed in to remove the walking part so that the breathing signal can be seen. Breathing amplitude is about 25 degrees, which equals 1.8 millimeters with the 5.6 GHz center frequency and breathing frequency is 0.25 Hz (15.3 breaths/min).

When I'm holding my breath signal is not completely flat, but instead a periodic signal can be seen that is caused by heart beat moving my chest a tiny amount.

Zoomed in to heartbeats.

Zoomed in further to heartbeats.

Amplitude of the heartbeat signal varies a little bit because of random motions. Heartbeat frequency is 1.1 Hz (65 bpm). Amplitude is about 1 degree which translates to motion of 75 µm.

Same measurement with empty room.

Above is the result of same measurement but with empty room for measuring the phase noise. Measured noise is much lower than the heart beat signal and we can be confident that it is not noise. It should be noted that measured signal was filtered digitally with 10 Hz low pass filter to decrease the noise. Unfiltered phase noise at full bandwidth is about 1 degree RMS.

In the phase noise plot small amount of drift can be seen. Source of this drift is probably clock drift between PLL reference clock and ADC clock. Clocks are drifting tiny amount because especially the RF board uses lot of power for its small size which heats it up and when crystal is heated its frequency changes slightly. They should be derived from same clock so they wouldn't drift respect to each other, but I didn't realize it when drawing the schematics of the radar. Luckily drift is very minor and it doesn't cause many problems in normal operation.

Homemade synthetic aperture radar

2015-10-14T00:00:00+03:00

Finished radar boards without antennas.

Introduction

Previously I made a very simple frequency-modulated continuous-wave (FMCW) radar that was able to detect distance of a human sized object to 100 m. It worked, but as it was made with minimal budget there was a lot of room for improvement.

Non-linear frequency sweep causes decreased resolution.

One of the bigger problems was that voltage controlled oscillator (VCO) generating the high frequency output signal was driven directly from the digital-to-analog converter (DAC) of the microcontroller. VCO tuning voltage and output frequency relation is not linear and using a linear ramp as a tuning voltage generates slightly non-linear frequency sweep. If the frequency sweep is not linear it generates non-constant mixing tone at the baseband. FMCW radars use Fourier transform of the baseband signal to find the distance to the target and when the received tone is not constant it spreads the power in the frequency domain and target resolving resolution decreases.

VCO's output frequency as a function of the tuning voltage. Ideally this would be linear.

A linear sweep can be generated by pre-distorting the VCO tuning voltage so that result is a linear sweep. Drawback of this method is that it requires knowing the exact VCO voltage/frequency characteristics which varies to some degree as a function of temperature and from component to component. Other way is to use a phase locked loop (PLL) that uses a frequency divider to measure generated RF frequency and compares it to accurate low frequency reference oscillator. A feedback loop then adjusts VCO tuning voltage so that divided frequency equals the reference oscillator frequency, this forces the RF signal frequency to be division amount times the reference oscillator frequency. Sweeping the divider value in small fractional steps can be used to generate a very linear sweep. Alternatively reference oscillator frequency can be swept while keeping the divider constant.

Mixer output of the old radar when antennas are replaced with loads. Waveform is caused by the LO leaking to RF input port of the mixer.

Receiver also had few problems. First being that baseband low frequency amplifier just didn't have enough gain to amplify low power echoes from far away limiting the maximum range. Other receiver problem was DC mixing product changing during the sweep and creating AC signal.

Receiver LNA had a gain of 13 dB and mixer after it had a conversion loss of 8.5 dB. This only leaves 4.5 dB of gain at RF section and causes the baseband low frequency signals to have very low amplitude. Since the receiver is a direct conversion receiver, LO oscillator leaking to RF input port of the mixer is going to cause a mixing product at DC. Power amplifier output power and mixer conversion gain vary with frequency causing the DC offset term to also vary. It creates an AC signal with frequency equal to sweep repetition frequency. This frequency is around 1 kHz and is amplified by the baseband amplifier. Since RF gain is low, this leakage signal can have bigger amplitude than the received signal saturating the baseband amplifier. A better mixer with more isolation, PA with less gain variation, more gain at RF and high-pass filter after mixer can be used to minimize this effect.

Last problem was with the microcontroller. It was not fast enough to transfer all the ADC samples to PC through USB. It was able to transfer only 25 sweeps/second while radar would take 500 sweeps/second. It probably would have been possible to improve firmware but strict timing constraint for generating the VCO ramp signal would had made it hard.

Because of the various problems with the old design I decided to make a new radar that fixed the problems.

New radar

Block diagram of the new design.

The new radar design is very similar to the old one on system level, but with few improvements. It functions using same principle: Transmitted linear sweep reflects from target and is received at the receiver. There it is multiplied with copy of transmitted sweep. Since electromagnetic radiation travels at speed of light, there is a time difference between received reflection and transmitted sweep. Multiplication in mixer generates a low frequency signal that has a frequency proportional to travel time of signal. Fourier transforming the mixer output signal gives frequencies in the signal and it can be used to resolve more than one target at the same time.

Biggest difference is addition of PLL that linearizes the transmitted sweep. PLL used is ADF4158, it is designed especially for radars and it can be programmed to generate accurate sawtooth and triangular ramps.

Other changes include: much faster microcontroller, better receiver, better baseband filtering and various other small improvements.

Bare PCBs.

Design is split it two boards. One has digital functions and other high frequency parts. One of the reasons was that if I made a mistake with the PCBs, with two board design I could probably only order one new board and save money. Two boards also reduce the noise going from digital board to RF board.

RF board needs to be four layered, because 50 ohm transmission lines would be too wide on 2 layer board because of thicker substrate. Four layer board is also made out of better material with lower loss and more stable parameters. Digital board could be made with two layers to save money as four layer board costs two times as much as two layer board for same area.

But it turns out that two layer board would need to be bigger as compact BGA components can't be routed on two layer board and bigger QFP packaged microcontroller would be needed. QFP takes more than four times as much area as BGA, so using BGA on four layer board turns out to be cheaper. It also enables packing the other components closer and results in better routing with less interference due to having more layers available.

Schematic. Click for PDF.

Digital board

Microcontroller PCB in KiCad without zone fills.

First I was thinking of having FPGA for signal processing, but they are expensive and don't have easy and cheap way to add high-speed USB communication. I ended up using NXP LPC4320 204 MHz ARM microcontroller. It has interesting serial GPIO (SGPIO) device that has several shift registers that can be configured very extensively. SGPIO can be used to implement communication protocols such as UART and SPI, generate PWM signals, interface to parallel output ADC which I'm using it for and various other things. SGPIO subsystem can be clocked up to 102 MHz allowing for very fast data transfer from ADC. Microcontroller also has high-speed (480 Mbit/s) USB, so this time the transfer rate shouldn't be a problem. It's also one of the cheapest microcontrollers with high-speed USB costing 7.2 € at low quantities at Digi-Key.

SGPIO slice block diagram. One slice can be configured as input or output, generate interrupts and clock source can also be configured. Slices can also output to other slices.

HackRF uses the same microcontroller for same reasons. Since HackRF is open source I'm able to use its software with small modifications. Existing software really helps especially as I don't have debug connector on board making it hard to see what the microcontroller is doing.

RF board

RF PCB in KiCad without zone fills.

RF board is based on the ADF4158 PLL chip. It takes a 30 MHz reference clock and RF output from VCO as inputs. VCO output frequency is divided by programmable divider on the chip and divided frequency is compared to reference clock. Chip then outputs analog voltage to VCO's tuning pin to makes the divided RF frequency equal to reference clock. Since low frequency reference clock and divider can be made very accurate and stable, PLL chip makes the VCO output frequency to also be very accurate.

This chip is made especially for radar applications. Its divider value can be fractional so that RF frequency can be stepped in smaller steps than multiplies of the reference clock frequency. It also has internal function that can automatically step the divider value so that it generates linear sweeps ideal for radar without needing constant control from the microcontroller.

Mixer LO coupler. A small portion of the power amplifier output is coupler to mixer. Small footprint on right side is for 50 ohm resistor terminating the other branch of the coupler.

Coupler simulated S-parameters. S11 = input from PA, S31 = Coupler power to mixer and S21 = Power passed to antenna.

Previous radar used passive mixer with high local oscillator power requirement. Wilkinson divider after the PA was used to divide output power equally to antenna and mixer. Mixer wouldn't have needed that much power and it caused reduced efficiency and lower radiated power.

New coupler couples much less power to the mixer (-16 dB = 3%) and much more is passed to the antenna. Simulated power loss from power amplifier to antenna connector is only 0.23 dB (5%).

Reason for using sharp 90 degree bends with part of the corner cut off is that these corners are designed to minimize reflections of the bend. These kinds of corners are called mitered bends. Large diameter smooth bends could also have been used, but they take more space. Mitered bends are also used on the long trace to mixer local oscillator input.

Low noise amplifiers. Receiving antenna SMA-connector on the top right, balun and mixer input at the bottom.

This time there is additional amplifier after the LNA to increase the gain before the mixer. Active mixer I'm using has a higher noise figure requiring more gain than the previous passive mixer to achieve low system noise figure. Noise figure of the system can be calculated using Friis formula. If only the first LNA would have been used noise figure of the system would have been 6 dB. With two LNAs noise figure is 2 dB.

ADL5801 active mixer.

Instead of passive mixer like last time with high LO power requirement, this time mixer is active. It requires less LO power which enabled using coupler instead of power divider. Conversion gain is also bigger which increases the output signal level at the baseband. Better isolation between LO and RF ports also reduces the DC-offset term.

Possible downside of using active mixer when downconverting to low frequencies is higher flicker noise from higher amount of transistors needed compared to passive mixer. At lower frequencies transistors generate much more noise than at high frequencies and below some process dependent corner frequency this noise behaves like 1/f increasing sharply when frequency decreases. MOSFET transistors typically have much higher corner frequencies, sometimes several megahertz in case of small integrated transistors. Bipolar transistors usually behave much better and they have corner frequency typically few kilohertz. If the mixer was made with MOSFETs it might have high 1/f noise causing the noise figure calculations to actually be much higher. Mixer I used was made with SiGe process which uses bipolar transistors. It doesn't have low frequency noise characteristics in the datasheet, but it probably has low enough corner frequency to not matter at this application as the baseband signal frequencies are around 10 kHz to 1 MHz.

Range compensation high-pass filter

Baseband filter schematic. IF is output from mixer, IFF is input to ADC driver.

Received power by radar decreases as a fourth power of distance. This causes various problems, such as doubling the maximum detection distance requires 16 times more transmission power. Other problem occurs when there are several targets large distance apart. Target close to the radar reflects much more power than the farther target. Fourth power means when target is 10 timer farther, power received is ten thousand times smaller. Real hardware has limited dynamic range making it possible that close target with more powerful return signal masks the weak signal from farther target.

Because the frequency of the target in FMCW radar depends linearly from the distance to the target, it is possible to use high-pass filter to equalize the signals from far apart targets. If signal after the mixer is filtered using 40 dB/decade high-pass filter, responses from same sized targets from different distances will ideally have same amplitude.

In schematic above is a 40 db/decade high-pass filter implementing the range compensation. The first stage is LC-lowpass filter to filter out the high frequency noise before the first amplifier stage. After AC-coupling capacitors for removing the DC-offset is the first amplifier stage that amplifies the signal before more processing. Next stage is a 2nd order Sallen key high pass filter that generates the 40dB/decade slope. Output then goes to digital board which has a variable gain stage and ADC driver.

Baseband filter frequency response.

Downside of this approach is that at low frequencies baseband gain is much lower and it can even attenuate the signal. RF noise is still same at all frequencies, so low baseband gain reduces the dynamic range at low frequencies. In the end it doesn't really matter that much since at low frequencies dynamic range was already very high due to high received power.

Below is the same scene is simulated with and without the range compensation filter showing how big effect it can have.

Simulated received signal after mixer from several same sized targets at various distances.

FFT of received signal. Target very close to radar reflects so much more power that targets farther away are not seen. X-axis is frequency in Hz.

Same signal after range compensation filter.

FFT of filtered signal. Targets farther away are now also visible.

Soldering digital board

Backside has only few passives and is soldered by hand.

Backside is soldered first. It has only light components that stay in place by surface tension of the solder even while upside down during reflowing of the top side. Board-to-board connector is soldered after the top side is done, it is so tall that it would raise the board and make applying solder paste on the top side harder.

100 ball BGA footprint. Solder mask is applied slightly offset.

Spreading solder paste using stencil.

Close up of the BGA before reflow.

I managed to put the BGA pretty much perfectly on place, there's maybe about 0.1 mm of positioning error, but surface tension of the solder can correct it. Even bigger positioning error should be fine as long as balls don't bridge the solder paste drops.

Outline of the BGA on solder screen is very useful for positioning it. Without any visible guide on the board positioning would be very challenging as the pads are under the chip.

After reflow.

After reflow solder joints look good. It looks like the solder balls on the BGA also reflowed and combined with solder paste on the PCB. If only the solder paste reflow with balls staying solid everything might work for a while, but the contact between ball and small amount of reflowed solder paste isn't very reliable.

After reflow.

Chip on left is flash memory for firmware, center is microcontroller, right is ADC and below it is op-amp to drive it. Unpopulated component on the bottom left is USB power switch for USB on-the-go. I decided to leave it out since it can be switched from the microcontroller. If it is enabled while connected to computer it would short the on-board 5V to computers USB power line, which is why it's better to leave it out until everything else is working.

Two very small surface mount switches are reset button and USB bootloader button.

Microcontroller working. Other LED is controlled by the microcontroller.

Advantage of two board design is testing in parts. If there was a mistake in power supply circuit that would provide too much voltage, at least the other board would be saved.

Soldering RF board

Backside of RF board.

To save money I didn't order stencil on bottom sides of the boards. There are only passive components with leads visible that are easy to solder without stencil. On top side are all the difficult to solder components which are much easier using stencil.

Paste on RF board. Missed a spot on top left corner.

Paste on RF board after removing the stencil.

Components soldered. Tabs on the sides are leftover from manufacturing of the PCBs, they could be snapped off but I haven't done it yet.

Shiny traces without solder mask are controlled impedance lines for high frequency signals. Solder mask would cause some additional loss and slightly change the impedance of the lines so it's better to remove it, though effect isn't very big.

Last time the traces were quite rough which probably had some effect on the matching. This time edges of the traces are etched very smoothly.

Jump wires and transistor.

Somehow everything ended up working without any bigger mistakes. One small mistake I made that required a jump wire was wiring the ramp complete pulse from PLL to general input of microcontroller. I was thinking I could put a pin-change interrupt on the pin, but this ended up not working. SGPIO buffers the samples from ADC so that it's not possible to know the exact sample that ramp was completed from interrupt. I had to connect also the ramp complete signal to SGPIO input and sample it for every sample from ADC.

This required adding a transistor to lengthen the pulse as input isn't anymore edge triggered. Pin is connected to the drain of the transistor with integrated pull-up resistor of the sourcing current and parasitic capacitance of the board slowing the signal. Luckily I had added a test pad to one of the unused SGPIO inputs, otherwise fixing it would have been impossible due to BGA package.

Also visible in the picture above is glob of hot glue holding the boards together. Mounting holes would have costed at least 10€ more in PCB costs so I decided to leave them out.

Range measurements

Image of the football field.

Easy way to measure radar range is to have radar pointing at empty area and then walk back and forth in its field of view. From the radar data it's then easy to see how the signal-to-noise ratio changes as distance to radar increases.

Time-range plot of me walking down a football field. Bandwidth was 700 MHz.

Above is a time-range plot of me walking back and forth a football field above. Lines around 35m are reflections from a football goal. Beyond 80m is a fence, some bushes and buildings which have large radar cross-section.

For antennas I used the same horn antennas I made for the previous radar.

Compared to same test from previous radar signal-to-noise and range resolution ratio are much better. Improved range resolution is caused by much larger bandwidth and more linear sweep. Increased bandwidth also increases signal-to-noise ratio as there is less clutter per range cell. More sensitive receiver has a big effect on the signal-to-noise ratio and because of range compensation both near and far targets are visible at the same time.

Reducting clutter by substracting the previous sweep from the next one.

Subtracting previous sweep from the current one in time domain should remove all the static targets since they should generate exactly same return. Small targets are removed, but some of the biggest are removed only partly.

When I'm close to the antenna, I'm shadowing the background which changes its reflection and doesn't cause completely perfect subtraction.

Wind can move the leaves a bit, even a millimeter of the movement will change phase of the signal and not cause complete subtraction. That's why my track is visible even though my movement between sweeps is only about one centimeter.

Clock drift between PLL reference and ADC sampling clock will also cause the subtraction to not be completely perfect. PLL reference and ADC clock are separate, but should have been derived from the same source for best accuracy. The small drift between them will cause phase of the baseband signal to vary a little and subtraction is not perfect.

Time plot of the baseband signal. Y-axis is raw ADC values.

Above is the raw baseband signal from ADC. Due to high pass filter high frequency returns from far away targets and low frequency returns from near have about same amplitude.

Fourier transform to get distance.

Taking Fourier transform of the ADC output gives the distances. This is from the beginning and reflection around 9 m is from me. Signal-to-noise ratio is about 60 dB.

Zoom around 9 m.

Resolution of radar depends on its bandwidth with higher bandwidth giving better resolution. It should be noted that resolution only means being able to detect nearby targets as separate. Accuracy of the distance depends only on accuracy of clocks of the radar. Padding signal with zeroes smooths the FFT and allows to locate the peak with much better accuracy. Zooming into the 9 m peak reveals that my position at that moment was about 9.43 m. Unfortunately I don't have means to verify this to required precision.

Synthetic Aperture Radar

Besides measuring the distances, radar can also be used to generate two-dimensional images of the scene. This can be done by measuring several distance profiles while radar is moved on a straight line with antenna looking sideways from the direction of travel. If the antenna radiation pattern is very narrow, range profiles can be stacked to make image of the scene. Issue with this method is that assumption about the narrow beam width can't often be fulfilled. Antennas I'm using have beam width of about 40 degrees and resolution in direction that radar was moved (cross-range or azimuth) would be horrible.

SAR system diagram. As radar moves along the line targets inside the antenna radiation pattern change.

Synthetic aperture radar is a signal processing method of achieving much better cross-range resolution from same range profile measurements. It uses many range profile measurements along a line to synthesize antenna that is as long as the line radar moved in. Beam width of an antenna is related to its physical size and very long synthesized antenna has very small beam width giving much greater cross-range resolution.

Airborne SAR system diagram.

Typically SAR imaging systems are mounted on either airplane or satellite so that it can look at large area of ground from angle. Radar sends pulses to ground which reflects them back and gives information about distance to the scene being imaged.

To get reflections from the ground and avoid shadowing from big structures antenna of the radar needs to be mounted in angle. If angle is too big and antenna points straight to ground range resolution is poor since all of the reflections come from almost same distance away. If angle is low and antenna points along the ground then tall structures such as buildings and hills can hide other objects behind them and flat objects like ground don't reflect signal back to the radar since reflection angle is too shallow.

Unfortunately I don't have a spare airplane so I mounted the antenna on bicycle pointing in zero angle. This means that only tall vertical structures like lamp posts, building walls and trees reflect the signal and image looks like cross-section of the imaged area.

Radar mounted on bicycle for SAR imaging. Antennas have started to rust a little.

To properly focus the SAR image, platform (bicycle) needs to move at constant speed in straight line, this is relatively easy to do even on bicycle if ground is flat. Antenna should also point in the same direction. Tilting the bicycle will cause it to point to ground or sky and change the radar return. Tilt of few degrees shouldn't affect the image too much because of large antenna beam width.

Hard part is that path needs to be very straight because phase of the return signal is used for focusing the image. Phase of the baseband radar signal wraps around when radar moves half wavelengths of the carrier frequency. In this case carrier frequency is about 5.5 GHz making the wavelength 5.5 cm. To be properly focused error in path linearity should be around less than tenth of a wavelength, which is only 5 mm. It is very challenging to move in this straight line for several meters and some amount of defocusing from movement is expected.

Cross-range size of the image depends on the length that platform traveled, but going larger distance also means that motion errors are larger which increases defocusing of the image. Proper SAR imaging systems use GPS and very accurate and expensive inertial measurement units to measure the actual motion of the platform and take it into account when focusing the image. Phone GPS doesn't have high enough resolution and I don't have inertial measurement unit so I just needed to try my best to keep constant speed and straight path.

I decided to try taking a SAR image of the nearby football field where I tested the radar before. Right next to it is paved road that is very flat minimizing the motion errors.

Raw unprocessed data.

Camera image of the football field. Taken next day, bicycles weren't in the SAR image.

Above is the raw range data from radar before SAR focusing. As expected the method of just stacking range profile doesn't result in very high resolution image. Format is the same as in stationary range-time plots before but now the radar is moving. Y-axis is range in meters and X-axis is samples. Sweep time was 2 ms, track was about 30 m long and bicycle speed was approximately 1.4 m/s. This works out to one sweep every 2.8 mm and for signal processing it can be assumed that radar was still while sweeping. This is called stop-and-go approximation and it simplifies the signal processing. Only every tenth sweep was used for image focusing.

SAR focusing algorithms are a big topic that you could write a book about. In short there are several algorithms for focusing SAR images designed for different imaging geometries. The one I'm using is omega-k algorithm, which is also called range migration algorithm.

When radar moves along the line targets on the radiation pattern of the antenna stay visible for some distance on the line. Because radar measures direct distance to the target, returns from the target shows as arcs due to changing distance to it. These arcs are very clearly visible in the raw data image above spanning wide area of the image due to wide antenna radiation pattern. Before cross-range focusing can be done this range migration must be corrected.

Omega-k algorithm corrects the range migration using process called Stolt interpolation on the Fourier transformed raw data. As a result energy from same target is lined on a same range cell and inverse Fourier transform can be used to focus the image. More detailed explanation and mathematical derivation can be found in example from this thesis[PDF]

SAR image of the football field.

Above is the resulting focused SAR image of the same raw data above. Resolution is greatly increased and now some of the features of the scene can be seen. Still lack of focus can be seen especially on the fence posts in the middle of image. Each post is smeared in cross-range direction several meters due to motion errors during the imaging.

Camera picture above is taken at +8m cross range. Bigger fence post of green metallic fence on the left in the camera image have high radar cross-section and are very clearly visible in the SAR image. Bicycle racks are visible as lines. Radar signal passes relatively easily through the trees on the foreground, but metal fence at the end of the field at 120m reflects very strongly. Still some of the signal goes through it and reflects from building across the street.

To focus the image better, I wrote a minimum entropy autofocusing[PDF] program. When image is in focus it is sharper and its entropy is lower. Minimum entropy autofocusing algorithm picks a phase shift for each sweep that minimizes the image entropy.

Autofocused SAR image. Click to enlarge.

Autofocused image is much sharper. Now the fence posts have much better resolution, but there are still some places in the image that are not perfectly focused.

Motion error from autofocus.

Calculated motion error is few centimeters. Most of the remaining lack of focus is probably caused by non-constant speed of the bicycle as autofocusing algorithm can only correct motion error in range-direction.

Note that autofocusing algorithm didn't enforce any continuity or other structure on the phase error. Still the solved phase error is very physically reasonable. Antenna couldn't have moved too much during the few milliseconds between the sweeps and phase error difference between adjacent sweeps is small as expected. I find it surprising that using optimization goal as simple as entropy of the image works this well.

Overlaid on aerial photo. Red line is the line of movement. Goals on field have moved since taking the picture.

When overlaid to image of the field from Google maps, SAR image agrees well with it. Football goals have moved a little since map has been updated, but everything else is where it should be.

Conclusion

Total cost was about 200€. PCBs were 28€, components were about 120€, battery pack was 21€ from China and antennas were made from scrap metal.

All hardware design files, firmware and processing software is available at github.

Horn antenna for radar

2015-02-22T00:00:00+02:00

Introduction

For background about the radar, read the article here.

Since the previous can antenna wasn't very good I made a better horn antennas. Horn antenna is a good choice for a radar antenna for many reasons most important being the very wide bandwidth and it's easy and cheap to make.

CST Model

I made few different antennas and I ended up with this small horn antenna. Aperture is 100mm x 85mm and length of the antenna is 90mm. Bigger would have been better, but would have needed more sheet metal and thus costed more.

Simulated gain is 14.4 dB and 3 dB beam width is 35 degrees. For comparison old cantennas had gain of 6 dB, beam width of 100 degrees and much higher sideband levels, so these new antennas should be significantly better increasing range and reducing clutter.

Horn antenna model in CST.

Simulated farfield radiation pattern.

Simulated gain.

Simulated S-parameters.

Fabricated antenna

Antennas are made from 0.7mm sheet metal with pieces welded together. Quality could have been better and there is more than 2mm tolerance at some places, it is probably big enough to affect the performance. Base is made from a piece of extruded aluminium that I picked from trash.

I also put a piece of sheet metal between the antennas to reduce the antenna to antenna coupling but it didn't seem to have much effect.

Fabricated horn antennas.

Front view. Feedline can be seen in the middle.

Measurements

I measured input reflection coefficient with a network analyzer.

Right side antenna S11.

Left side antenna S11.

Due to tolerances in manufacturing there are some differences in the input reflection coefficient, but most importantly with both antennas S11 is below 10 dB for the whole usable frequency range of the radar (about 5.4 GHz to 6.1 GHz). When compared to the simulated S11 above it's clear that the shape of the curve roughly agrees, but especially at higher frequencies there are big differences with real antennas actually working better than simulated.

Tests with radar

I tested the antennas with the radar at the same football field as with the previous antennas. The goal in the middle of the field that caused the targets near 50m with old antennas was removed but the surrounding trees and fence were still there.

This time even without the clutter reduction (subtracting previous pulse to get rid of stationary targets) results are much better. Looking at the signal strength near the radar it's clear that new antennas have much higher gain. From the lack of clutter it also seems that beam width is also now much narrower. The path were I walked is clear even before the clutter reduction unlike with the previous antennas.

Time-range plot with new antennas and no clutter reduction

Same measurement with the old cantennas.

Measuring the beam width

To know the exact beam width better I made a measurement where I walked perpendicular to the radar beam.

Picture of the radar and surroundings with path I walked in red.

Beam size measurement results.

Above is the measurement results and near 80 second mark small red blip can be seen when I was inside the radar beam. I measured from that my walking speed is about 1.4 m/s. Time I was inside the beam such that it could be differentiated from the background was about 6.5 seconds. From the above plot we find that the distance to radar is 11 m. From these numbers we can calculate that the beam width of the radar is about 44 degrees. Since this is not 3 dB beam width but more like 10 dB beam width it agrees well enough with the simulations. For comparison beam width of the old cantennas was more than 100 degrees.

In conclusion the radar works much better with proper antennas. Range is increased, but the football field isn't long enough to test it. More importantly smaller beam width decreases the amount of clutter picked up from the surroundings and greatly increases the signal to noise ratio.

6 GHz frequency modulated radar

2014-12-02T00:00:00+02:00

Finished radar board without antennas.

Introduction

I've for some time now wanted to do more RF design. Although I have taken some RF design courses, I haven't actually made a single RF design before. But you can't learn without doing and inspired by the MIT coffee can radar designed by Gregory Charvat, I figured that building a radar should be a doable project that would offer some challenge while also having some real world use.

The simplest radar is a continuous wave Doppler radar, which continuously transmit a constant frequency signal. This signal reflects from a moving target and Doppler shift causes reflected signal to change frequency. This reflected signal is then received and mixed with the transmitted signal. Mixer product is the difference of the frequencies which is proportional to the speed of the target. This kind of radar is very simple to make, in fact there are even some children's toys. Unfortunately it can't detect the range of the target and isn't that exiting.

A little more sophisticated radar which can detect also the range can be made by modulating the frequency of the transmitted signal. This kind of radar is called continuous wave frequency modulated radar (FMCW radar).

Radar transmits a chirp, which increases linearly with the frequency. This chirp is then radiated with the antenna, it reflects from the target and is received by the receiving antenna. On the reception side received and undelayed copy transmitted chirps go to the mixer. Because received chirp reflected from the target, but copy of the transmitted chirp is undelayed there is delay between the signals. This causes mixer output to have a low frequency signal which frequency depends on the distance to the target. When there are several targets the output signal is sum of different frequencies and the distances to the targets can be recovered with Fourier transform.

FMCW radar block diagram

Glossary of the terms in the block diagram:

MCU - Microcontroller
VCO - Voltage controller oscillator
PA - Power amplifier
LNA - Low noise amplifier
ADC - Analog to digital converter
FFT - Fast Fourier transform

Transmitted signal is: $f(t) = sin\left( 2\pi\left(\frac{f_0 + f_1}{t_{\text{ramp}}}t+f_0\right)t\right)$ and the received signal is a delayed copy of it, $f(t-t_d)$. Mixer multiplies these signals, outputting two frequencies which are the sum and difference of the multiplied signals. These can be solved using the trigonometric identity: $\sin\phi \sin \theta = \frac{1}{2}\left(\cos(\phi-\theta)-\cos(\phi+\theta)\right)$. Sum frequency is too high to be detected and is filtered out. Frequency of the difference term gives: $f_{\text{diff}} = \frac{t_d (f_1-f_0)}{t_{\text{ramp}}}$. Since electromagnetic waves travel at the speed of light delay of the received signal is twice the distance to the target divided by the speed of light. Distance to the target in terms of the detector frequency can be solved to be: $d = \frac{c f_{\text{diff}} t_{\text{ramp}}}{2(f_1-f_0)}$.

For example with $f_0$ = 6 GHz, $f_1$ = 6.1 GHz, $t_{\text{ramp}}$ = 5 ms, $d$ = 100 m the output detector output frequency is 13.3 kHz, which is low enough to be detected with very cheap equipment. Even a PC soundcard would have enough bandwidth and this is actually how the MIT coffee can radar works.

How about the Doppler shift? It can be found out in two ways. If the frequency waveform is sawtooth wave, then we can take multiple consecutive range measurements and then take another FFT over them. Because movement of the target also changes the distance to it speed can be recovered and distance corrected.

Another way is to modulate the frequency with triangle wave. Doppler shift causes the mixer output frequency to be different depending on whether the frequency is increasing or decreasing.

Schematic. Click for a pdf version.

Board layout in Kicad without zonefills

Designing the radar

For radar applications high frequency is needed for smaller resolution. High frequency also allows using smaller antennas because wavelength is smaller. Unfortunately going to too high frequencies is going to get too expensive, component selection starts to be very limited and the RF design starts to also get much more difficult. 2.4 GHz would be very easy and cheap to design for because there are many different and cheap components for this frequency range due to it being used for many different purposes such as WLAN, microwave ovens, radios and more. Another frequency range where there also exists some more use and cheaper components is 5 – 6 GHz range which is used for 5 GHz WLAN. Going higher than that and there isn't that much general applications and the components are going to be very expensive. 6 GHz range is also still quite easy to design for and parasitic losses aren't yet too high to demand using exotic substrates and components.

Normal FR4 board isn't very good for RF design, since impedance is not controlled and there can be significant variations from board to board which makes accurate designing impossible. Only cheap manufacturer that offers board with controlled impedance is OSH Parks four layer process which uses FR408 substrate with a dielectric constant of 3.66.

This board is not ideal for RF design, since spacing between the first and second layer is only 0.17 mm. This leads to very thin traces (50 ohm microstrip is 0.35 mm wide) but they are still within the manufacturing tolerances so there is no problem.

Microcontroller

Kinetis KL26Z128VFT4

I wanted to have a microcontroller with a USB interface, so that it would be easy to interface with the PC doing the heavy processing. Integrated ADC and DAC would also be nice to save some board space and money.

The cheapest microcontroller having all these was Freescale Kinetis KL26Z128VFT4. It has an ARM Cortex-M0+ core that can be clocked at 48 MHz. It costs 3.4€, has USB, 16-bit ADC and 12-bit DAC. Though, when you actually read the datasheet ADC only haves about 13 effective bits without the hardware averaging. It isn't a big downside, since even 13-bits is very good precision for this price. I didn't notice it before ordering the board, but there is another catch with this processor: it only supports USB 1.0. In theory full-speed USB 1.0 can transfer at 12 Mbits/s which would be enough, but in practice this is not reached and only about five sweeps of 1000 samples can be transferred in a second, which gives a transfer speed of about 10 kB/s.

Transfer speed can be almost doubled quite easily by compressing the transferred signal. Since the signal is smooth, difference between two consecutive samples is small. This makes it possible to only transfer the difference to the last sample in one byte. In some cases the difference doesn't fit in one byte, this can be worked around by using a special value (I used all ones) for byte, which is used to signal that two bytes long full sample value follows. In practice this works really well and difference overflows only a few times in full sweep and about ten 20 ms long sweeps of 1000 samples can be transferred in a second. I believe that with more software optimization slightly higher speeds could be reached, but 10 sweeps per seconds works well enough that I haven't bothered yet.

From the software perspective this was very interesting processor. Kinetis offers a Processor Expert tool that can generate the driver code for the peripherals automatically. This makes configuring clocks, ADC, I2C and all other peripherals much easier and it works really well also in practice. There are some things that it doesn't support, for example changing the timer speed at runtime is not possible. Still, it's always possible to use the registers directly to implement the missing functionality.

I had much difficulties in programming this board, programming would succeed only very rarely and most of the time programmer would either fail to recognize the processor or fail to write to the flash. I even managed to brick one microcontroller so that it couldn't be programmed anymore. The cause turned out to be that this processor requires capacitance at reset pin. I couldn't find a note about this on the datasheet, but without it programming is not reliable. When looking at the reset line with the scope it seems that processor will generate a sawtooth signal on it. It seems that without the capacitor processor will reset itself too quickly for the programmer to connect. After adding a 100 nF capacitor to the reset pin everything started to work reliably.

RF portion

VCO and PA input

RF signal is generated by the voltage controlled oscillator (VCO), which tuning voltage is generated by the microcontroller. Output power of the VCO is 2 dBm, but because this power would be too much for the power amplifier attenuator needs to be places before the PA to attenuate the input signal so that it won't saturate the amplifier.

Discrete microwave frequency VCOs don't seem to be very common components and selection is very limited. VCO is the most expensive component in the whole radar costing 17€ a piece.

In the picture you can also see a MOSFET that allows the PA to be switched off by cutting of the bias voltage to it. 0 ohm resistor was put there to allow replacing it with a bigger resistor to drop the bias voltage if needed.

PA and power divider

The reason I chose to use 5 – 6 GHz band was because there is a band reserved for radars around 5.8 GHz and this range overlaps with 5 GHz WLAN. Since wifi components are very common, there are many different cheap choices for the power amplifier. PA I chose to use is SST11LP12 which is a cheap WLAN PA costing 1.5€. There would haven been cheaper PAs, but their datasheets were so short on the details that I didn't dare to use them.

PA is the component using most of the power on the board. Supply current is about 400mA from 3.3V. Since this is supposed to be a somewhat portable device and I don't want to include big batteries the power and communication is done over the USB. Maximum current draw of the USB device is 0.5A from 5V. This means that the PA uses about half of the available power. Since other components don't use nearly as much there shouldn't be a problem with USB powered operation.

PA amplifies the -2 dBm signal from the VCO to 21 – 23 dBm (0.1 – 0.2 W) signal depending on the frequency. Output signal then goes to the Wilkinson power divider, which divides the output to the transmitting antenna and the mixers input port. Since full divider output would be too much for the mixer a 7 dB attenuator is added before the mixer to attenuate the input signal to more manageable level.

LNA and mixer

Radiated power is reflected from the target, captured by the receiving antenna, amplified by the low noise amplifier and then mixed with the PA output signal. LNA is also meant for the 5 GHz WLAN. It has a very low noise figure while also being incredibly cheap costing only 1.1€ at small quantities.

Amplified received signal is then passed to the mixers RF port, where it's mixer multiplies the PA signal and the received signal. IF port of the mixer then outputs two frequencies: difference of the input frequencies and the sum of the input frequencies. Sum frequency is over 10 GHz which exceeds to mixer output frequency and doesn't need to be worried about. Difference signal is the wanted result signal and it has a frequency of about 100 Hz to 10 kHz.

Baseband

Variable gain amplifier

After the mixer output signal has a very small amplitude in about microvolt range and must be first amplified before filtering can be done. First amplifier uses LT6230 low noise op-amp in a non-inverting amplifier connection. MCP4017 is a I2C controlled variable resistor and varying it's resistance varies the gain of the amplifier. Gain is $1+\frac{\text{R5}+\text{R(MCP4017)}}{\text{R9}}$.

Input signal is has some small DC offset that depends on the antenna to antenna coupling, but it should be around zero volts. Since I wanted to do this as cheap as possible I chose not to use dual supplies for the amplifiers. This means that signals DC offset needs to be rebalanced to 1.65V which is half of the op-amps supply voltage. Rebalancing is done with the capacitor C17 that blocks the DC voltage and resistor R3 which is connected to the 1.65V setting the signal DC level.

This works, but is not a very good solution. Resistor attenuates the signal and increases the noise at the input. In hindsight using two supplies would have been a better solution without increasing the cost by more than few euros.

DC balancing has also another issue: Since the balancing is done with a resistor the DC voltage at the input won't be exactly 1.65V. Amplifier has a high gain and it will also amplify the DC offset causing the output voltage DC offset to be off.

I noticed the issue before ordering the boards, but my solution of adding another DC blocking capacitor after the filter is not really a good solution since it doesn't fix the bad balance after the first amplifier. A better solution is to make the gain frequency dependent by adding a series connection of capacitor and resistor (R0 and C0 in the picture) in parallel with R9. DC won't flow through the capacitor and the gain is set by the R9. AC will flow through the capacitor and gain is set by the parallel combination of R9 and the resistor R0. I found that setting R9 to 1.5k and adding 44 uF capacitor and 50 ohm resistor worked well. This solution is not without downsides, R9 contributes most of the noise in the amplifier and increasing it will also increase the noise. It doesn't matter much though, since turns out that due to bad antennas gain can't be turned big enough for it to reach the noise floor.

Antialiasing filter

Because signal is going to be sampled by the ADC, filtering is needed to ensure that highest frequency of the signal is less than half of the sampling frequency, so that aliasing doesn't occur. Filter itself is the same as the one used on the MIT coffee can radar. Cutoff frequency is 15 kHz, but it could have been higher since the microcontroller can sample at least at 200 kHz. In practice it doesn't matter since range of the radar is not enough to generate a 15 kHz signal.

Filter is also not very good. It's a low pass filter, but since higher frequencies are generated by the targets that are farther away filters gain should increases with the frequency until the cutoff frequency. This way the weak higher frequency signals are amplified more and the dynamic range of the radar increases.

Single ended to differential conversion circuit

Using a ADC with differential input gives a better resolution than using a single ended input with the microcontroller that I'm using. The circuit above is straight from the LTC6242 datasheet and it will convert the single ended signal from the filter to differential signal for the ADC.

This circuit also had some unexpected problems. LTC6242 is rail-to-rail op-amp, but when I tested the circuit output saturated already at 2.6V even though operating voltage is 3.3V. Cause for this turned out to be the common mode voltage range of the inputs. 2.6V is the maximum voltage that should be applied to inputs and higher voltage than that will saturate the inputs and the output responds as if the input voltage was 2.6V.

Fix for this isn't too complex. Some gain needs to be added to the circuit so that the 2.6V input generates 3.3V output without any inputs voltage exceeding 2.6V. This is possible by adding a resistor Rx in parallel with C21. This attenuated feedback signal to the first op-amp which causes its output to increase output voltage so that the feedback voltage at negative input equals the input signal at positive input. Full voltage of the first op-amps output won't be applied to the second op-amp and the circuit will work correctly with full output swing.

Power splitter

Wilkinson power splitter

Power splitter is a Wilkinson divider. It's lossless divider with good isolation between the ports, but it is frequency dependent. If the signal is too far off from the design frequency isolation between the ports suffers. Frequency range that radar uses is not too big for this to matter too much and it works fine. One disadvantage in this application is the equal division of the power. We would like most of the power to go to the transmission antenna and only a little bit to the mixer. With equal division there needs to be an attenuator before the mixer to make decrease the input power. This is a wasted power that should be used in transmission. More complicated power splitter would add too much board area to be worth it, even the simple Wilkinson splitter uses large amount of the board compared to how many components could be fit into the space it uses.

I would have liked to use smooth bends in the splitter since they are simple to design, but Kicad doesn't support them. So instead I had to use 90 degree mitered corners. Mitered corner is just a bend with a cutout on the corner which negates the impedance change from the bend. They are very often used in microwave circuits since they don't reflect the signal and can be fit into smaller space than smooth bends.

Solder mask is also removed from the top of the traces so that it doesn't affect the impedance. It also has a side effect of making the traces look much cooler since the beautiful gold plating is visible. Large number of vias are required to connect top and bottom ground planes together. Wavelength at 6 GHz is about 36 mm, distance between the vias needs to be much smaller than this so that there isn't potential differences in the ground planes. A common rule of thumb is that the distance between vias should be 1/20 of the wave length. Since adding more vias doesn't cost anything I were generous in placing them and the distance between vias is about 1mm around the RF traces.

First version I designed used the usual design equations: Impedance of two divider traces is $\sqrt{2}\times 50 \approx 71~\Omega$ and the length is quarter of the wavelength, which equals about 8mm.

Since I had a access to CST microwave studio, I decided to simulate the divider with it. CST has a handy feature that allows importing the gerber files so the simulation model dimensions are exactly as drawn in KiCad.

Power divider modeled in CST. Blue cylinder is 100 ohm resistor and red planes are waveguide ports.

Simulated S-parameters.

Divider was designed to have a center frequency of 5.5 GHz, but according to the CST it's working best at 6 GHz. Adding 1.2 mm more length shifts the working frequency to 5.5 GHz. I guess the difference is caused by the fact that I calculated the trace length from the branch to the center of resistor pad, but I believe length of the trace should be calculated from the branch to the center of the resistor.

From the low S11, -35 dB at best, it can be seen that the mitered bends are working and only a minimal amount of power is reflected back to the input. Though even with a straight 90 degree bends without miters reflections at these frequencies are most likely going to be minimal since wavelength of the signal is much bigger than the corners.

S21, gain from PA to transmitting antenna is -3.3 dB. Ideally it would be -3 dB, which equals even split of power with nothing being wasted, but especially substrate losses consume some of the power. 0.3 dB extra loss is still a very good figure.

S-parameters after adjusting the length.

With the adjusted trace lengths port isolation is below -20 dB at all usable frequencies (5.3 GHz to 6.3 GHz).

SMA connector interface

SMA connector modeled in CST

With ordinary low frequency design something as simple as connector doesn't really require any attention. However, things are different with RF frequencies. To minimize the loss in microstrip to coaxial cable transition I decided to simulate also this interface. The potential issue with the connector is that the 1.3 mm center conductor is much bigger than the 0.35 mm microstrip that should connect to it. Since connector pin needs few millimeter solder pad to solder the pin, the pad itself works as a microstrip and since it's so wide it has a very low impedance and there is a significant impedance discontinuity between the microstrip and coaxial cable which reflects the power back.

There are connectors that are more suitable for these track widths, but these are the cheapest SMA connectors and even they are quite expensive costing 3€ a piece. Better ones would have costed about 10€ a piece, which would have been a significant part of the total cost.

Simulated S-parameters.

Simulation confirms that the there is an issue. S11 is -3 dB at 6 GHz, which means that half of the power goes to antenna and other half is reflected back. But this doesn't mean that this connector cannot be used, it only requires some changes to interface. Issue is that the solder pad works as a microstrip and it has a wrong impedance. Making it thinner would solve the problem, but it's not possible or connector can't be soldered. The other solution is to make a cutout to the ground plane. Because impedance of the microstrip depends on the distance to the ground plane below it, making a cutout to the ground plane below the pad will raise its impedance and eliminate the impedance discontinuity.

After few simulations turns out that the optimal cutout is 3.7x2.6 mm and with it the S11 is -22 dB, so hardly any power (0.6%) is reflected back.

Ground plane cutout.

S-parameters with a cut ground plane.

Soldering the board

Bare PCBs from OSH Park

Beautiful purple PCBs from OSH Parks.

Close up of the PA and power divider.

Some roughness can be seen on the thin power divider 71 ohm trace edges. It's not very good for performance since width of the trace affects its impedance. Roughness is still low enough that the effect to the impedance should be minimal.

Spreading the solder paste with stencil from OSH stencils

Paste for the QFNs can be applied by hand, but I'd rather avoid it if possible. Using stencil just makes applying the solder paste so much easier and saves so much time that it makes sense to order a stencil even when making a single board since they are so cheap.

After applying the solder paste.

A very good spread of the paste. There was a slight misalignment of the stencil, but it isn't big enough to matter.

Placing the components manually.

I could really use microscope with some of the smallest components, but I managed to place all the components even without one. 0402 passives are still kind of pain to use, but they save board space and are required for RF reasons in some places.

Close up of the soldered PA.

After five minutes in the oven paste has reflowed and components are soldered. Soldering with the reflow oven is just so good that I wonder how I once managed without one. Solder joint quality is just so much better than manually soldered and oven gets the job done much faster.

Backside also had some components.

For the smallest board (and cheapest price) both sides of the board need to be used. I planned on not ordering a stencil for the backside so there are only few passive components which I applied the solder paste manually.

Board with the components labeled.

Finally above is a picture with the different components labeled. Unlabeled components on the center are: 3.3V regulator for analog components, 3.0V regulator for VCO and LNA and op-amp to for generating 1.65V virtual ground for the baseband filter.

VCO VTUNE amplifier is needed to amplify 3.3V DAC output signal from microcontroller to 10V.

Testing the board

Output spectrum at full sweep bandwidth. 20 dB attenuator at the output.

Above is the spectrum analyzer output when radar is VCOs tuning voltage is swept full range from 0 to 10V. Output frequency goes from 5.6 GHz to 6.3 GHz. Since there is a 20 dB attenuator at the output, real output power is 15 dBm. This includes the loss in the 1m SMA cable which should be around 1 dB at these frequencies.

Output power is not quite even and drops actually 6 dB over the range. This is expected and follows the specifications in the PA datasheet. Maximum gain is achieved already at 4.0 GHz and it drops by about 10 dB at 6 GHz. This amount of gain unevenness is not a problem since sweep bandwidth is around 100 MHz and drop over this bandwidth is low.

Theoretically input power of the PA is -5 dBm and gain is about 27 dB at 6 GHz, so the output power should be 22 dBm. Since the power divider has simulated loss of 3.3 dB the output power should be 18.7 dBm minus the unknown loss in the cable. Measured power is not quite the calculated one, but it's close enough to say that the PA and divider are working as designed.

Antennas

With the board done it's time to make the antennas. Usually radars use very directional horn antennas. Directionality of the beam is important so that only signal from the target is picked up instead of the surroundings. Besides the directionality radar antenna should have low sidebands so that antenna to antenna coupling is low and it doesn't pick up reflected signals from behind and sides of the radar. Also the antennas should not reflect the power back but instead do their job and radiate it.

Maybe one of the best antennas would be a pyramidal horn antenna. It can fulfill all the specifications, except that manufacturing is expensive. I didn't want to spend too much money in making a very good antenna when I wasn't sure if the radar board would work. So instead I decided to first make cheap and crappy antennas to test the board and maybe then manufacture proper antennas.

So I decided to make antennas out of cans. Can antennas are more commonly known as cantennas. Problem with most of the cans is that they are too big for 6 GHz range. 33 cl soda can would be good but they are made out of aluminium which I don't have equipment to solder. Most promising cans I found were two quite small cans originally containing canned pears.

Model of the cantenna in CST.

Simulated farfield directivity pattern.

The only free parameters with the cantenna design is the location of the SMA connector and length and the diameter of the SMA connector center wire. Even though I tried to optimize them as best I could, not surprisingly performance of the cantennas is really bad. Beam width is 100 degrees, which is really wide for a radar antenna. Simulated radiation pattern is also quite weird, there is a hole right in the center of the main beam and no matter how I adjusted the feed position, feed line length or its diameter I couldn't get rid of the hole without sacrificing radiation efficiency.

Farfield with constant phi of 90 degrees.

Farfield with constant phi of 0 degrees.

As can be seen from the above, the hole is pretty deep. It's a pretty bad antenna but it should be enough to test if the radar works.

Simulated input reflection.

Input reflection is decent, anything below -10 dB should be fine.

Finished cantennas.

Closeup of the SMA connector.

Best way to solder the SMA connector is to first remove the teflon insulator and just solder the shell first. It's easier to position if the teflon piece is inserted from the wrong side so that it comes out to the inside of the can. Then the teflon piece will center the shell into the hole, which makes soldering it much easier. After soldering the shell feed wire needs to be soldered to the center conductor of the SMA connector. This is also easier to solder with the teflon piece removed. After soldering the feed the teflon piece can be pushed back from the outside.

I was first worried if the soldering iron would have enough power to heat the can hot enough, but there weren't any difficulties in soldering the connector with a regular soldering iron and a regular solder wire.

Inside view showing the feed.

Measured input reflection. X-axis is frequency from 4 to 6 GHz and y-axis is S11 with 10dB/div.

I also measured the S11 of the real antenna using network analyzer. It had a maximum frequency of 6 GHz so it was just barely enough. Measured S11 is -15 dB at 6 GHz, which is actually better than a simulated value. This might be the first time that something works better in real life than simulations. Both of the antennas have pretty much identical S11, so manufacturing tolerances probably can't be blamed. Reason is probably the caused by the simplistic model which didn't include the ripples in the can. Those would have been too time consuming to make, so I just modeled the antenna with smooth walls. Shape of the S11 still agrees closely to the simulated shape suggesting that the simulations are not too inaccurate.

Radar with the antennas.

Finally I taped the antennas to a supporting plate and connected the radar board.

Outside testing

Football field and the radar.

Above is a football field where I tested the radar. I used a carboard box to raise the antennas from the ground. In the picture radar is behind the PC.

Usually radars have very directional antennas so that they can be pointed accurately at the target without too much reflections coming from the surroundings. Since the antennas that I'm using have a beam width of about 100 degrees, radar is going to pick up a lot of reflected signals, also called clutter, from the surroundings.

View from the other side of the field. Cardboad box can be seen in the center with radar on top of it.

Above is the view from the other side. Box under the radar can be seen at the middle, but radar isn't really visible at this distance.

Range-time plot without clutter reduction

Above is the processed signal plotted as time in seconds on y-axis and range on x-axis. Colors are the power of the detected frequency referenced to some arbitrary value.

There's a quite lot of clutter in the foreground from the trees at the sides. Some of the clutter is also caused by the reflections from sides and behind of the radar via sidebands of the antennas. Around 50 m clutter from the goals in the middle of the field can be seen clearly and at around 130 m is clutter coming from the buildings at the background. It's quite hard to see, but especially at the foreground a diagonal line of my path can be seen.

Range-time plot with clutter reduction

After subtracting the previous pulse from the current one all the stationary clutter is cancelled and suddenly things are much more clearer. Signal to noise ratio is about 15 dB at 50 m and goes to zero near 90 m. There is still quite a lot of noise due to clutter not being completely canceled. For example wind moving trees and inaccurate sampling causes the consecutive pulses to not be completely identical and there is some clutter left even after the subtraction.

Capture of one sweep. ADC range is scaled from -0.5 to 0.5.

Above is one of the captured waveforms and it's clear that everything doesn't seem to be right. There is a very big peak at the beginning of the sweep which limits the maximum gain of the automatic gain controller to about one third of the maximum gain. If the peak and the low frequency signals wouldn't exist, the gain could be increased which would also improve range of the radar.

Mixer output captured with an oscilloscope.

Looking at the oscilloscope capture of the mixers output it's clear what the cause is. Low frequency high amplitude signals caused by the reflections close to the antenna cause very big discontinuity at the start of every sweep. Since this signal is AC coupled to the baseband, it will cause a decaying peak after passing through the capacitor. Fix would be to use better antennas.

So in summary the radar works and the range is not too bad, though it could be easily increased with better antennas and I thats what I'm going to start working on next.

All hardware design files, firmware and processing software is available at github

Making embedded Linux computer

2014-07-10T00:00:00+03:00

All of the best integrated circuits today come in hard to solder BGA packages. Because BGA packages have connections under the chip soldering is harder and it needs to be done using a reflow oven or hot plate. Another problem is with designing the PCB, vias and traces need to be small enough to fit between the solder balls and there needs to be usually quite many layers in the board to make room for all the closely packed traces. This means that a cheap Chinese two layer board doesn't have enough room and more layers are needed. Adding layers increases the cost of the board dramatically when ordering only a few copies.

I wanted to try designing a board with BGA chips in it to see how hard soldering them could be. So I decided to design a small ARM embedded system that can run Linux. ARM processor that I decided to use was AT91SAM9N12 in a 217 ball LFBGA package, just because it was the cheapest ARM processor with memory management unit which is required to run Linux. Originally I wanted to have only one BGA chip, but RAM in BGA package was significantly cheaper than in other packages and I decided to also have DDR2 memory in a BGA package.

Positioning VIA for maximum amount of space.

Finding a manufacturer for the board turned out to be a slightly challenging task. Two layers wouldn't be enough and at least four layers would be needed. Ball diameter of the 217-LFBGA package is 0.4 mm and distance between adjacent balls is 0.8 mm. To make a little bit more room for the vias ball land pattern can be made slightly smaller than the solder ball. I used 0.36 mm pads. Putting via between the four balls maximises the available space. Manufacturer needs to be able to make a via that fits in about 0.8 mm space. Almost any manufacturer can make a via with this diameter, but the problem is that this distance includes via drill diameter, two times the annular ring around the via and two times the minimum distance between via and trace. For example iTead's four layer board has minimum via drill diameter of 0.3 mm, minimum annular ring width of 0.15 mm and minimum 0.15 mm between via and trace. This adds up to 0.9 mm which means that minimum sized via can't fit between the BGA balls. The only reasonably priced manufacturer I found was OSH parks. Their four layer board has smaller limits and via can just barely fit between the BGA balls. As a bonus it's also cheaper than iTead for small board.

Minimum via with OSH park design rules, fits just barely

Even though the via can fit between the BGA balls, there are still some problems: There is not enough room for trace to go between two vias. This means that it's not possible to route the BGA using standard escape routing where every pad has one via. This means that board needs to have enough unconnected pads on the perimeter, so that traces from the inside can be routed. Fortunately the processor has many general I/O- pins that are left unconnected.

... but trace doesn't fit between two vias without violating the design rules. CAS trace doesn't have enough room to fit between DQM0 and D15 vias.

Manufacturing concerns solved, it's time to start thinking what components should be on the board. I don't really care about the usefulness of the board and this whole project is more of a learning experience. To keep the costs down board size needs to be kept small. This means that there won't be space for any extra interfaces like ethernet, serial ports or SD-card.

Besides the processor and RAM other essential components are: mass memory, voltage regulators and supervisor circuit for handling the reset of the chip. Processor can boot from the NAND, but I decided to also have Dataflash for the bootloader just in case, though this ended up being left unpopulated. For mass memory NAND flash is a good choice because it's cheap with big capacity. Having it also in a BGA package would have been cheaper, but I already have enough trouble with two BGA packages, so I decided to use 4Gb NAND in a 48 pin TSOP package.

Connecting the components is explained well in the processor's datasheet, but because the document is over 1000 pages long it might be hard to find all the details. Atmel also publishes schematics of the evaluation boards that are very helpful when designing a board.

Some freedom needs to be taken with DDR2 traces. Normally traces should be length matched, have controlled impedance and terminating or series resistors. Reference design from the development board uses series resistors in all of the DDR2's signals. I don't have enough room for them so I just decided to leave them out. Impedance isn't 50 ohms either, because I had to use smaller traces to fit everything. I hoped that because RAM is so close to the processor, lack of series resistors and impedance mismatch wouldn't matter. All traces from CPU to RAM are about 25 mm long. Usual rule of thumb is that if trace length is over 10 % of wavelength of the signal then transmission line effects should be taken into account. In this case it would mean that frequency should be roughly above 1 GHz. RAM clock frequency is only 133 MHz and even the first few harmonics are under the 1 GHz, which suggests that this should work fine. Just to be sure I matched the trace lengths within few millimeters, but this might have been unnecessary.

Voltage supplies are bit complicated. Processors core voltage is 1.0 V, RAM needs 1.8 V and NAND needs 3.3 V. Because the input voltage is 5 V from USB, board needs to have three different voltage regulators. Normally it would be good to reserve one layer on the board for power supplies and keep it free from signal traces to lower power supply impedance, but board only has four layers and one of them is used for ground plane. This would mean that there would be only two layers left for signals which wasn't enough. So I didn't have separate power supply layer and instead made several planes in different layers for different power supplies.

Losses with linear regulators would have been too big for USB powered applications in the worst case, so I decided to have 3.3 V regulator as a more efficient switching regulator. 1.0 V and 1.8 V regulators are linear regulators that have 3.3 V as input voltage. Because linear regulators losses depend on the difference between input and output voltage using 3.3 V as input instead of 5 V increases the efficiency.

Schematic. Click for a pdf version.

PCB layout. Copper pours are not filled.

Soldering

Bare boards.

Solder paste and components applied to backside. Paste was applied manually with a toothpick. Components here are 1 mm (0.04 in) long. I put only the passives first to see how they would reflow and if the results weren't good I could use another board.

Reflowing with a toaster oven and custom controller.

After reflowing. Three components were soldered in a wrong place. I just ended up taking them out, there are enough decoupling capacitors on the board and if few are missing there is not any negative effects. I also mistakenly placed a capacitor on the upper left footprint, but there should be a resistors instead.

For the topside I got a stencil from OSH stencils so I wouldn't need to apply paste manually to BGA footprints. I secured the board and stencil by taping them to the table.

Stencil lines up very well.

This might look excessive, but almost all of the solder paste is recovered. Some extra solder paste is needed to get even fill.

After spreading the paste and removing the stencil. Much better than the backside paste I applied by hand.

I started with non-BGA components. They are placed manually with tweezers and a steady hand.

CPU and my fingertips. Ball spacing is 0.8 mm. Many new BGAs use even smaller 0.5 mm spacing.

BGAs placed on the board. Component needs to be placed with less than 0.4 mm error or otherwise it might be soldered with one row offset and because solder balls are under the chip alignment cannot be checked. Without border draw on the silk screen it would have been almost impossible to place with required precision, with the silk screen it's easy to just line up the component border to the silk screen border.

Reflowing the top side. Geiger counter PCB are used to raise the PCB so that bottom side components don't touch anywhere. Solder surface tension will keep the bottom side from falling.

After the oven. Solder joints look very nice and all components are still at their places.

Soldering the NAND Flash. My solder iron tip is bigger than the pins and soldering one pin at a time was too difficult. Easier way is to flood pins with solder and then take the extra out with solder wick.

After removing the excess solder the solder joints are very high quality.

Finished board after adding the headers for power supply and debug serial port.

Final product with hand for scale.

The other side. Empty footprint is for Dataflash.

After plugging the USB cable to the USB device port nothing has exploded and I can see that a new serial port /dev/ttyACM0 has appeared and opening it with SAM-BA program, which is used to program the bootloader and kernel, everything seems to be working. Many people say that soldering BGAs is hard but based on this experience I can't agree. Maybe I just got lucky but I didn't have any problems with them.

Opening SAM-BA. At91sam9n12ek is Atmel's development kit for this processor and its configuration also works for this board.

DDR2 works, executing programs work and writing to NAND works. In other words everything works.

Software

Boot flow graph

Bootloader

Boot process start with internal ROM bootloader trying to find a valid program in different memories. It probes SPI flash, SD card, NAND flash, second SPI flash and I2C EEPROM for a valid program. If it finds one it starts it, otherwise it enters into SAM-BA monitor, which is debugging mode where processor listens serial and USB port for commands. This mode allows programming the bootloader.

ROM boot can't boot Linux kernel directly so a second stage bootloader is needed. It will initialize RAM and clocks and then load the Linux kernel. AT91 Bootstrap is a ready made bootloader that does all of this. It will be stored at the beginning of the NAND flash it could also be placed to Dataflash if I had populated its footprint. Even though AT91 bootstrap could boot Linux directly it's more useful for debugging to have U-boot bootloader after it. U-boot is its own mini operating system with command line and it can read USB sticks, use ethernet, write and read from NAND and of course boot Linux. Using U-boot makes it easier for example to erase NAND or change Linux boot parameters.

To compile the bootloader an ARM cross compiler is needed. I'm using Sourcery codebench lite edition, because it's very easy to set up and works well. It's easiest to first load AT91SAM9N12EK development board configuration file. Modifying this configuration file saves a lot of trouble compared to writing new configuration file from scratch.

To make it work for this custom board some changed are needed: RAM size needs to be configured to 64MB, number of banks changed to 4 and some latencies tweaked (Evaluation board has 128MB of RAM with 8 banks). NAND initialization function also needs to be modified, this board has NAND flash connected to different place than the development board and it's necessary to tell the bootloader about it.

U-boot

Configuring U-boot is very straightforward now that AT91 bootstrap has initialized the hardware. It also has configuration file for at91sam9n12ek, but it's set up to boot from SD-card by default. There aren't many other required changes to make, because hardware is already configured. Some optional ones are enabling UBIFS tools for creating and editing partitions on NAND flash and enabling support for reading ext4 formatted USB sticks. USB support makes it possible to boot Linux kernel from USB stick, which makes easy to experiment with different kernel configurations.

Linux and root filesystem

Installing Linux isn't as easy as with a regular x86 PC. Kernel needs to be configured to support all required devices and the root filesystem image needs to be built. This could be done by hand, but it's easier to use buildroot which is a set of makefiles for building the root filesystem and kernel. Still the process can be a little hard because of massive number of different options in kernel and buildroot.

Buildroot doesn't have configuration file for at91sam9n12ek development board, but it has a file for other Atmel board, at91sam9260ek. Using this configuration as a base will makes the configuration little easier. These settings can be loaded with "make at91sam9260ek_defconfig".

First we want to have a relatively new kernel version, because there have been some minor changes related to this processor. So let's use version 3.15.3, which was released last week.

Linux is configured in buildroot with "make linux-menuconfig" command. It will open the usual Linux menu configuration window. Most important configuration in the kernel is system type configuration menu. We need to check AT91SAM9N12 support and "Atmel AT91SAM Evaluation Kits with device-tree support" option. Device-tree is an external binary file that is loaded with the kernel which describes the hardware available on the board. This makes it possible to use same kernel with different boards and device configuration for different boards can be made using text files instead of writing slightly different C-files for every board. Luckily there exists a device tree file for at91sam9n12ek which can be used as a base. Required changes are basically removing the devices that are not available. Path to this modified device tree file needs to be added to buildroot configuration so that it knows to compile and build an image out of it.

Other options worth enabling in the kernel are:

USB host support AT91_USB.
NAND flash support and processor's internal NAND ECC controller (PMECC) support.
Support for UBIFS, which is going to be used as a root filesystem.
Ext4 support for reading USB stick.

In buildroot configuration we need to choose what programs we want to have on root filesystem and the options for generating the root filesystem image. This board has raw NAND memory without controller so usual desktop filesystems such as ext4 can't be used. UBIFS is the usual choice and it's also fine in this case.

UBIFS has several options that depend on the NAND flash type and if they are wrong Linux can't read the resulting filesystem. These options could be figured out from the NAND flash datasheet, but easier way is to boot Linux from USB stick and create ubi partition from there. Or alternatively use U-boot's "ubi info" command which will read the NAND and output the required configuration values.

After typing "make". Buildroot will download cross compiler, Linux kernel and all of the other packages; build them and output kernel, device tree and root filesystem images. These can be transferred to board with SAM-BA program. Same program is needed to program NAND ECC controller parameters. Same parameters should be also configured to AT91 bootstrap, U-boot and Linux kernel or otherwise they will report that NAND is corrupted. In this case NAND has 2048 byte pages with 512 byte sectors and ECC should be able to correct 4 bits per sector. NAND addresses to store all the images can be found in AT91 bootstrap and U-boot configuration files.

After programming the board and resetting, the ROM bootloader should find the AT91 bootstrap on the NAND and start the boot process:

Your browser does not support the video tag.

If you are interested in learning more, hardware and software files are available at github.

UPDATE 2014-08-10:

I ran memory test on the RAM and there were some errors. Rarely, about once per loop on memtest, there was an error on 19th bit on random write test.

# memtester 20M
memtester version 4.3.0 (32-bit)
Copyright (C) 2001-2012 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

pagesize is 4096
pagesizemask is 0xfffff000
want 20MB (20971520 bytes)
got  20MB (20971520 bytes), trying mlock ...locked.
Loop 1:
  Stuck Address       : ok         
  Random Value        : ok
  Compare XOR         : ok
  Compare SUB         : ok
  Compare MUL         : ok
  Compare DIV         : ok
  Compare OR          : ok
  Compare AND         : ok
  Sequential Increment: ok
  Solid Bits          : ok         
  Block Sequential    : ok         
  Checkerboard        : ok         
  Bit Spread          : ok         
  Bit Flip            : ok         
  Walking Ones        : ok         
  Walking Zeroes      : ok         
  8-bit Writes        : ok
  16-bit Writes       : ok

Loop 2:
  Stuck Address       : ok         
  Random Value        : ok
  Compare XOR         : ok
  Compare SUB         : ok
  Compare MUL         : ok
  Compare DIV         : ok
  Compare OR          : ok
  Compare AND         : ok
  Sequential Increment: ok
  Solid Bits          : ok         
  Block Sequential    : ok         
  Checkerboard        : ok         
  Bit Spread          : ok         
  Bit Flip            : ok         
  Walking Ones        : ok         
  Walking Zeroes      : ok         
  8-bit Writes        : |FAILURE: 0xfdb30157 != 0xfdbb0157 at offset 0x001892e4.
  16-bit Writes       : ok

Loop 3:
  Stuck Address       : ok         
  Random Value        : ok
  Compare XOR         : ok
  Compare SUB         : ok
  Compare MUL         : ok
  Compare DIV         : ok
  Compare OR          : ok
  Compare AND         : ok
  Sequential Increment: ok
  Solid Bits          : ok         
  Block Sequential    : ok         
  Checkerboard        : ok         
  Bit Spread          : ok         
  Bit Flip            : ok         
  Walking Ones        : ok         
  Walking Zeroes      : ok         
  8-bit Writes        : ok
  16-bit Writes       : |FAILURE: 0x7df4005f != 0x7dfc005f at offset 0x000b7778.

This probably means that the error is with D3 trace. It's the longest data trace and runs parallel to some address lines for short runs. Hard to say for sure what the cause is, but it is related to signal integrity as this chip should be able to run at 133MHz reliably. Despite the errors, this configuration worked well enough that no kernel panics or anything related to bad memory was observed during the normal operation. Issues seems to arise only when memory is stressed.

If clock speed is decreased to 100MHz memory seems to work fine. I have run memtester for over 10 hours consecutively and no errors have been found.

BSDL file to KiCad library converter

2014-04-27T00:00:00+03:00

Boundary Scan Description Language (BSDL) files are provided by many electronic component manufacturer for testing the pins of the microcontroller, FPGA or any other bigger device with JTAG. Even though they are meant for JTAG testing they can be used to generate device symbols for schematic designs, because these files list pins of the device and their locations on the chip.

Eagle has an ulp file that can generate the symbol from BSDL and I have used that with Eagle, but I wasn't aware of any similar tool for KiCad so I made my own. It's still a beta version so report any bugs you find.

Automatic generation is not perfect and some errors are common. BSDL files are not meant for this and often some unimportant pins for JTAG are left out, for example input voltage and ground pins, because testing them with JTAG is not possible. Also listed pin names are usually the first function of the pin, but in many devices one pin can have many alternate functions. Still BSDL files usually have most of the pins and user only needs to check that everything is correct and add alternate functions to pin names if needed. Creating a big BGA device symbol using BSDL files is significantly faster than doing everything by hand even if some manual checking is needed.

You can access the tool here.

Automatically generated AT91SAM9N12 microcontroller symbol. Input voltage and ground pins are missing because BSDL file didn't list them. Other than that pins are correct.

Simulating audio effects with SPICE

2013-12-08T00:00:00+02:00

Introduction

While I was looking at some audio effect circuit schematics at the internet, I though that it would be nice to try to simulate them SPICE first and listen them, before building them to confirm if they sound good or not. But there aren't any electrical simulators that can read and output audio files, so I wrote a program using Pythons wave module, which can read a wave file and output a list of time-voltage points. Ngspice's file source device can read this big list of points and output a voltage waveform that matches the audio signal. This servers as a input for the effect circuit. To hear the output another program is needed to convert the output trace to wave file, for this too I used the Pythons wave module.

Distortion effect

Overdrive 250 schematic.

This was one of the simpler distortion effects that I found. It's called Overdrive 250 and it's pretty popular guitar effect pedal. Schematic is from this site. Function is simple, first there is an AC-coupling capacitor and biasing circuit, because voltage supply is single sided. Op-amp is used as a non-inverting amplifier to amplify the weak input signal. R5 is really potentiometer that controls the gain. At the output there's an another AC coupling capacitor and two diodes that clip the signal. Bigger the signals amplitude is the more diodes clip and distort it.

Test audio signal is a clean guitar sound and it's from freesound.org made by user named Khoon and released under a very permissive Creative Commons 0 License, which basically says that the work is public domain.

First the output with 500k R5, which gives a milder distortion. Input amplitude matters very much, because it's multiplied by the gain of op-amp. In this recording input amplitude is 10mV. These clips are quite loud (as can be seen from the waveform), so check your output volume before hitting the play.

Decreasing R5 increases the gain and distortion:

Frequency spectrum effects of the distortion, made with audacity:

Spectrum of the clean signal.

Spectrum of the harshly distorted signal.

Above are the frequency spectrums of the original clean signal and the harshly distorted signal. Difference is not that great. Some low frequency signals are filtered by the AC coupling capacitors and distortion has created new higher frequency signals. Increase of the power over the whole bandwidth is an artifact of the SPICE to wav conversion. To avoid clipping, I chose the maximum amplitude of signal to have the maximum sample value. This changes the volume of the signal.

Real circuit would probably sound slightly different, but I think this is pretty good for a simulation.

Simulation is not real time. It takes about five seconds to simulate one second of audio at 44100Hz sampling rate. For longer simulations to save memory it's good to save only the output waveform using save v(out) SPICE statement.

Fuzz effect

Second circuit is fuzz circuit, which is very similar to the previous distortion circuit, except op-amp is replaced by discrete transistors.

Fuzz circuit schematic. Transistors model is BC108.

This circuits output is also greatly affected by the input voltages amplitude.

This one is simulated with 1mV input amplitude:

And this one is with 10mV input:

Result is very similar to the distortion circuit, mostly because of the similar diode clipping.

Diode clipper

Waveform of the diode clipper is much smoother than I excepted it to be. Of course this also depends on the voltage of the signal and parameters of the diodes. But even this fairly smoothly clipped signal has lots of high frequency harmonics.

Simulation of 1V 400Hz sine wave clipped with a pair of 1N4148 diodes.

Spectrum of diode clipped sine wave.

Source code

Source code for the both of the used programs is available here.

Toaster oven reflow controller

2013-09-08T00:00:00+03:00

Almost finished controller board. This one was soldered by hand.

Introduction

Nowadays many of the most "exiting" chips come only in leadless packages, such as BGA and QFN which are hard or impossible to solder just by soldering iron, because leads are under the chip where they can't be reached. These kinds of chips are usually soldered using reflow soldering. In reflow process solder paste is used instead of solder wire. It contains very small balls of solder in flux, diameter of the balls is just few micrometers. First this paste is put on the contact pads, then components are placed on the pads and whole board is heated in reflow oven where solder balls in the paste melt and attaches the components firmly in place.

Temperature profile in reflow soldering. Source: Wikipedia

For the solder paste to work correctly temperature of the oven must follow correct temperature profile accurately. If the temperature rises too quickly it can damage the components and if the temperature rises too slowly, too much flux can evaporate and the components aren't soldered reliably.

Real reflow ovens are usually expensive, like many other manufacturing tools, but ordinary toaster ovens can be used in reflow soldering with few modifications. They are much cheaper than real reflow ovens, but temperature cannot be set programmatically or accurately. External controller board can be used to control these ovens.

Reflow oven controller

Toaster oven reflow controllers have been done before many times (for example 1 and 2). I wanted to make a simple and cheap controller that wouldn't use outdated parts. Instead of buttons and dedicated display, it should use USB port for setting the temperature profile and monitoring the temperature if needed. This would be cheaper to make and easy to use. If the computer isn't connected, it should be able to be switched on by just connecting the power supply, load the temperature profile from non-volatile memory and run without user intervention.

Because the oven gets very hot, it's not possible to add any electronics inside it. Controlling is done by switching the power on and off rapidly with solid state relay that is connected on extension cord. Temperature is measured using thermocouple inside the oven. Microcontroller will read the temperature and output PWM signal for the solid state relay which can be used to accurately control the temperature of the oven.

1380W Toaster oven with convection. Bought second hand for 20€.

I decided to use ATmega8U2 microcontroller, because I'm familiar with AVRs and this is the cheapest AVR with hardware USB support.

Because oven can get pretty hot I needed to use thermocouple for measuring the temperature, instead of cheaper temperature sensors ICs. I use MAX31855 as a thermocouple-to-digital converter. This is the most expensive component in the board costing 6.21€ at Digikey, even the solid state relay from dealextreme was cheaper costing only 5.08€.

Schematic. Click for bigger view.

Unfortunately I made some mistakes with the PCB and wired the USB connector pins in reverse order. One trace was also left partly unrouted, when I accidentally removed part of it in Eagle before generating the gerber files. I didn't have tools to fix the USB connector traces, so I just cut them out and soldered an USB cable on the board. Missing trace was replaced with enameled wire.

Extension cord with solid state relay before adding tape.

Board with USB cord and wire to fix the unrouted trace.

Firmware

Program reads the current temperature of the oven from MAX31855 chip through SPI, at the same time the chip also gives room temperature and signals if there is any faults with the thermocouple. State machine is used to get the current reflow state and target temperature. Every second current and target temperatures are outputted through USB port to computer for logging if it's connected.

On the computer side the microcontroller looks like a serial port and commands can be sent and read with any serial port program. If computer isn't connected microcontroller starts the reflow automatically with profile loaded from EEPROM.

PID controller is used to adjust the relay PWM signal, but because the oven responds very slowly the derivate component of the PID isn't very useful and the controller works really as a PI controller. This microcontroller, like many other cheap microcontrollers, doesn't have native floating point unit, so all arithmetic is done without floating point numbers to save program space.

Microcontroller has 8kB of program space and code uses 92% of it. Most of it is taken by USB library and printf function and the control code takes only about 10%.

Testing

Controller testing with a made-up temperature profile. Green is the target temperature and blue is the current temperature. Relay was fully on between 170 - 320 seconds, but oven couldn't heat fast enough to reach the target. Oven door was opened after the peak was reached to speed up the cooling.

Controller works like it should, but the oven doesn't heat fast enough to accurately follow the proper reflow soldering profile. This should be fixable by adding some insulation to the oven. Currently it has only small empty space between outer case and oven chamber.

Reflow soldered 0603 resistor.

Reflow soldering works, but I have only tested with 0603 resistors right now. Quality is good, much better than I'm able to solder by hand. Also if the component isn't placed straight, surface tension of the solder pulls the components almost perfectly straight when it's reflowed.

Board design and microcontroller source code is available at github. The PCB on github has USB connector wired correctly and all the traces routed.

Bill of materials

Component	Cost/€
Oven, used	20.00
PCBs, 10pcs	7.78
MAX31855 thermocouple-to-digital IC	6.21
Solid state relay	5.08
ATMega8U2 microcontroller	3.05
Thermocouple	1.59
3.3V regulator	0.33
Extension cord	3.00
Other components	about 2.00
Shipping+VAT	9.02
Total	58.06

I made a Geiger counter

2013-05-01T00:00:00+03:00

Ionizing radiation is something that almost anyone finds exciting (or scary) and I've also been for long wanted to build a Geiger counter. Unfortunately Geiger tubes have usually been too expensive to seriously consider buying them just for a hobby project. But I found out that sovtube sold soviet cold war era Geiger tubes only for a couple dollars. I bought one CI-22BG tube and one CI-3BG tube for total of 16€ including shipping from Ukraine to Finland. The site itself didn't really convince me payment via Paypal failed because of invalid seller email address and gmail warned me that order confirmation e-mail might not have come from the address it claimed. However, I got both of the tubes and they seemed to be okay.

Two Geiger tubes. Longer one is CI-22BG and smaller one is CI-3BG.

Because I didn't have anything radioactive to test my Geiger counter, I also ordered a piece of radioactive Fiesta dinnerware from ebay. Red Fiestware used to have uranium oxide in its glaze that was radioactive enough to be detected with a Geiger counter.

Two pieces of slightly radioactive fiestaware.

Geiger tube needs a high voltage, my tubes need 400V, to function. We need also a microcontroller to count the events and maybe a LCD to display the output. Also no Geiger counter is complete without a buzzer. I decided to also have USB port now that I included a microcontroller.

Schematic

Circuit schematic of the Geiger counter. Click for bigger view.

The device can be powered by USB or external voltage source. Circuit on the upper left corner, which was copied from this Stack Exchange answer, is responsible for choosing the right power supply. It will use USB if it's connected, otherwise it'll connect the external power supply. IC1 is step up converter that will increase supply voltage to 7V, or pass it through if it's already over 7V. This will allow the device to work with even 2V external voltage. IC3 is 5V low dropout regulator, that will regulate 7V to 5V for microcontroller. At the center there's the high voltage supply that will output 400V from 7V input. It runs in a closed loop with microcontroller adjusting the duty cycle to get a stable output voltage.

Normally Geiger tube will pass only a small leakage current, but when ionizing radiation hits the Geiger tube some of the gas inside the tube is ionized which will allow higher current through the tube, 4.7M anode resistor R10 limits this current to a safe value. This current will raise voltage at the base of T4 turning it on which pulls the detect net low. Then the microcontroller interrupts at the pin change and counts one event.

High voltage supply

High voltage supply schematic. R18, R19 and C13 are for feedback to microcontroller. R9 and C5 are used to filter the output and R10 is Geiger tubes anode resistor.

Because I wanted the device to work with USB the input voltage is 5V and this needs to be raised to 400V. Many other Geiger counter high voltage supplies use some topology that includes a transformer, but because transformers are big, heavy and expensive I didn't want to use them. At first I wondered if ordinary boost DC/DC converter running in discontinuous mode would give high enough voltage gain, so I made some test on a breadboard and with right components I managed to get 444V from 5V input voltage, which is more than enough to drive a Geiger tube. It could have gone to even higher voltages, but I was already over the SF16 diodes 400V breakdown voltage and 450V was upper limit of Geiger tubes working voltage. With a better layout on the PCB output voltage can reach over 500V.

Testing HV supply with 5V input voltage. This circuit uses SF16 diode, which should have a breakdown voltage of 400V, but looks like it can handle a little bit more. Mosfet is FQN1N50C.

I tested several different transistors and diodes. For mosfets, on resistance and switching speed were most important parameters. I didn't manage to get the only high voltage BJT I had, MSP44, to work at all. Because boost converter works in discontinuous mode, reverse recovery time of diode is important to minimize leakage. 1N4007 diodes were garbage at this application, BA159 was okay, SF16 was even better, but it's breakdown voltage was only 400V. Highest output voltage was with Cree CSD01060 600V silicon-carbide schottky diode. Because it's schottky diode it has only neglible reverse recovery time. Difference between 1N4007 and CSD01060 was about 100V, which is quite significant. With schottky diode output had hardly any noise and with 1N4007 noise was so bad that Geiger tube event detection circuit triggered every time mosfet was switched. I ended up using BA159, because of its high breakdown voltage and small footprint compared to CSD01060. Schottky can also have bigger reverse leakage than ordinary silicon diode. It's important in this application to keep it small, because available current at the output is already very small.

Switching transistor had an even bigger effect:

Voltage gain as a function of duty cycle with AOD3N50 mosfet. Input voltage was 1.2V for these tests. Voltage gain is low, because gate voltage was only 5V. Mosfets on-resistance at that gate voltage is too high to discharge the inductor fast enough, using higher voltage would have most probably raised the voltage gain.

Same with FQN1N50C mosfet. Output voltage was very unstable at high duty cycles.

I couldn't get MSP44 BJT to work at all.

PCB

PCBs from iTead. All of them looked fine. LCD connection and Geiger tube mount limited the minimum size of the board, so I had plenty of room to place the components.

PCB was designed with Cadsoft Eagle and manufactured in China by iTead, they were the cheapest PCB supplier I found. I decided to use mostly SMD components wherever possible, resistors and capacitors are in 0603 package. I was little sceptical if I would manage to solder them with my not so good tools, but it in the end it wasn't hard at all. I might even consider using 0402 package on my next projects.

I made the high voltage side using through hole components, because all of the SMD resistors I looked at claimed a maximum working voltage of about 200V, when I needed at least 400V.

Total cost was about 50€ including shipping costs. PCBs cost 21€ including shipping and for that price I got 12 of them. Atmega8U2 was single most expensive component costing 3€, other components together cost about 15€ and the Geiger tubes were 16€. Looking at the prices for Geiger counters at eBay, I don't think it was very expensive and building at least 10 at the same time would about halve the price.

Design is open source. Hardware design, PC software and microcontroller software are available at Github.

With components and 2€ coin for scale. I had to change the inductor on bottom right corner, because the inductor that I originally chose turned out to have so much coil noise, that it was almost louder than the buzzer.

Testing the Geiger counter

Your browser does not support the video tag.

Fiestaware piece I have shows about 700 counts per minute, depending slightly on how close to the tube I hold it. Background radiation level is about 10 CPM. I don't know how to convert CPM to any SI units with this tube, but according to the eBay seller I bought the fiestaware piece it should have radioactivity of about 20-30µSv/hr. Background radiation level should be about 200-400nSv/hr. Ratio of these numbers is approximately 80, which is about the same as I measured.

Datapath of my PIC16F84 microprocessor clone

2013-03-14T00:00:00+02:00

PIC16F84 is old 8-bit microprocessor made by Microchip. It was once very popular among the hobbyists, because of its low price. It was the first microprocessor I started to use so I thought it would be fun to try remaking it in VHDL. The source code is open source and can be found on my github.

I first started writing a single cycle design, but converted it to two-staged pipeline, because the real pic16f84 uses this kind of architecture. Two stages are fetch/decode and read/execute/writeback. For performance reasons it would be wise to have even more stages. With three stages separating the writeback to is own stage would increase the maximum clock frequency the most, but complicate the design and make some instruction take more time to complete in clock cycles than on the real version.

Simplified datapath and control signals. Signals not related to the program flow are removed.

PIC16F84 has very simple accumulator based architecture. There is only one accumulator register called W. Instructions are decoded to few control signals that control the multiplexers and other datapath elements. I don't know exactly how the microchips real version works, but I think it's very similar.

Executing the instruction start with fetching the instruction pointed by the program counter (PC) from the instruction RAM. Next it will be decoded to control signals that are used to control the datapath. Control signals go through a flip-flop that buffers them and allows decoding and executing two different instructions at the same time, better known as pipelining. Then the datapath reads RAM, executes the instruction and writes the result back if needed. This is the critical stage that limits the clock rate of the whole microprocessor. It would be advantageous to divide this pipeline stage to two or three seperate stages for higher clock frequency.

Control unit is responsible for stalling the exeuction state when needed, computing the new program counter and handling the interrupts. On call instruction or interrupt the current PC will be pushed on the stack and it will be popped from there on return instruction.

Control signals

Signal	Function
amux	ALU B-port multiplexer control signal
bmux	ALU A-port multiplexer control signal
writew	W <= ALU result, when this is 1
writeram	ALU result is written into memory location pointed by the current instruction
aluop	ALU operation, possible operations are: pass A-port, AND, OR, XOR, NOT A, A-B, A+B, A<<1, A>>1, set bit, test bit and swap nibbles of A (low and high 4 bytes)
branch	1 if decoded instruction is call or goto
return	1 if decoded instruction is return, retfie (return from interrupt) or retlw (return and set W to immediate)

With these control signals we can implement all of the instructions. For example movlw instruction, that moves literal to W is implemented as writew <= '1', aluop <= Pass A and others zero. This moves the literal from instruction to ALU result and to the W register input.

bmux signal might seem weird, but we need constant 1 available to this port when incrementing or decrementing a memory location. This could be replaced with two new ALU operations, increment and decrement, but it would really synthese into very similar logic.

Constant 0 on the other ALU multiplexer is used for clear W and clear memory location instructions. Also instruction that moves W to RAM is implemented as adding zero to W and then writing the ALU result to RAM, this way we don't need an ALU operation that passes the port B to ALU result. This again reduces the number of ALU operations needed and makes the microprocessor a little bit faster.

Zero flag from ALU to control logic is used for conditional branches. This signal is 1 if ALU operation is zero. When the conditional branch is taken we need to discard the result of the next instruction that is currently on the decode stage. This is done by asserting the not skip signal, which forces the writew and writeram signals to be zero for the next clock cycle. The instruction is executed, but because the result is not written anywhere it doesn't matter.

Lessons learned

Pipelining can easily have some subtle errors. Like when writing to program counter register in the RAM it functions as a branch. Writing can be actually done directly to the right RAM location or indirectly through special pointer RAM location (FSR). Both need to be checked at the control logic to stall the execution state.

It is easier to use RAM that has asynchronous read, but block RAM in the FPGA has synchronous read. If asynchronous read RAM is required it must be implemented as distributed RAM. I converted my instruction RAM halfway through the design from asynchronous to synchronous,

process(clk, we, a1)
begin
if rising_edge(clk) then
    if we = '1' then
        mem(to_integer(unsigned(a1))) <= wd;
    end if;
    d1 <= mem(to_integer(unsigned(a1)));
end if;
end process;

RAM with synchronous read. Moving the "d1 <= mem(to_integer(unsigned(a1))); " one line down would make the read asynchronous.

I have still implemented the data RAM as asyncrhonous read and I don't think it's possible to make it synchronous without adding pipeline stage. Address to read is calculated in ALU so the data read would be delayed to the next clock cycle.

Testing, you can never have too much of it. I started testing first by writing short programs and checking their output manually. This soon turned out to be too time consuming, because I would manually need to check outputs of the programs after making changes. Modifying programs to write results of the operations to output ports and using assert commands to test the correct values turned out to be much easier.

I have heard that some people generate random programs and compare the output to reference implementation written in behavioral VHDL or other language. It would be a very effective way to find bugs, but writing the reference implementation would take too much time.

UART designed to be used with FSM

2013-01-12T00:00:00+02:00

Some time ago I needed an UART for a project. Things it needed to do were very simple and I didn't want to add a microprocessor to use UART and instead decided to just code a simple finite state machine to use it.

But I couldn't find a simple UART designed to be used with FSM. They add features I didn't need and were hard to use without adding a microprocessor. One of the simpler ones was RS232 UART from opencores. But it too was meant to be used with a microprocessor. Receive end signal and some other signals were high for more than one clock cycle, which made design of the FSM more complex. I could have added a rising edge detector, but I decided to change the UART implementation instead.

So I made signals to be high only for one clock cycle, transmission to start immediately when the transmission start signal was asserted and made baud rate generation more accurate.

The code, readme and one example is uploaded to github.

Generating normally distributed pseudorandom numbers on a FPGA

2012-10-23T00:00:00+03:00

The other day I was coding an FPGA design that needed a source of normally distributed random numbers. Uniformly distributed random numbers are fairly easy and cheap to generate with a linear feedback shift register, but generating normally distributed numbers is a harder problem. There are several ways to generate a normally distributed number using one or more uniformly distributed, some are more accurate than others. For my purposes the numbers don't need to exactly follow the normal distribution,, it's enough if it seems like for a normal human that the numbers are from the normal distribution.

So I went for the easiest and cheapest implementation and use the central limit theorem, which says that summing sufficiently many independent random numbers result will be approximately normally distributed. I went for the sum of four uniformly distributed random numbers generated by a linear feedback shift register. To avoid obvious period in the output I decided to have a rather large 31-bit registers. 31-bits because it's big enough and it needs only two taps when a 32-bit register would need four.

Code for the linear feedback shift registers:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity random_uniform is
    generic ( SEED : STD_LOGIC_VECTOR(30 downto 0):= (others => '0');
                 OUT_WIDTH : integer := 11);
    Port ( clk : in  STD_LOGIC;
           random : out  STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0);
           reset : in  STD_LOGIC);
end random_uniform;

architecture Behavioral of random_uniform is

signal rand : std_logic_vector(30 downto 0) := SEED;
signal feedback : std_logic;

begin

feedback <= not((rand(0) xor rand(3)));

process(clk,reset)
begin
if reset = '1' then
    rand <= SEED;
elsif rising_edge(clk) then
    rand <= feedback&rand(30 downto 1);
end if;
end process;

random <= rand(OUT_WIDTH-1 downto 0);

end Behavioral;

Implementation of the linear feedback shift registers is very straight forward. Seed value and output width can be set with generics making it also useful in many other places.

Summing four of these uniform random numbers should generate number that is almost normally distributed. Code for the normally distributed pseudorandom generator is below, it outputs 12-bit signed numbers every three clock cycles, but it should be easy to modify it to work in one clock cycle just by adding more adders.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity random_gaussian is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           random : out  STD_LOGIC_VECTOR (11 downto 0));
end random_gaussian;


architecture Behavioral of random_gaussian is

component random_uniform is 
generic ( SEED : STD_LOGIC_VECTOR(30 downto 0);
             OUT_WIDTH : integer);
port(
    clk : in  STD_LOGIC;
    random : out  STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0);
    reset : in  STD_LOGIC);
end component;

component adder_signed is
    Port ( clk : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (11 downto 0);
           b : in  STD_LOGIC_VECTOR (11 downto 0);
           r : out  STD_LOGIC_VECTOR (11 downto 0));      
end component;

signal uniform1 : std_logic_vector(9 downto 0);
signal uniform2 : std_logic_vector(9 downto 0);
signal uniform3 : std_logic_vector(9 downto 0);
signal uniform4 : std_logic_vector(9 downto 0);

signal adder_a : std_logic_vector(11 downto 0);
signal adder_b : std_logic_vector(11 downto 0);
signal adder_r : std_logic_vector(11 downto 0);

type statetype is (s0, s1, s2);

signal state, next_state: statetype := s0;

begin

unif1: random_uniform 
generic map (SEED => std_logic_vector(to_unsigned(697757461,31)),
                 OUT_WIDTH => 10)
port map(
    clk => clk,
    random => uniform1,
    reset => reset
);

unif2: random_uniform 
generic map (SEED => std_logic_vector(to_unsigned(1885540239,31)),
                 OUT_WIDTH => 10)
port map(
    clk => clk,
    random => uniform2,
    reset => reset
);

unif3: random_uniform 
generic map (SEED => std_logic_vector(to_unsigned(1505946904,31)),
                 OUT_WIDTH => 10)
port map(
    clk => clk,
    random => uniform3,
    reset => reset
);

unif4: random_uniform 
generic map (SEED => std_logic_vector(to_unsigned(2693445,31)),
                 OUT_WIDTH => 10)
port map(
    clk => clk,
    random => uniform4,
    reset => reset
);

adder1 : adder_signed
  PORT MAP (
    a => adder_a,
    b => adder_b,
    clk => clk,
    r => adder_r
);

process(clk, reset)
begin

if rising_edge(clk) then
    if reset = '1' then
        state <= s0;
        random <= (others => '0');
    else
        if state = s0 then
            random <= adder_r;
        end if;
        state <= next_state;
end if;

end if;
end process;


process(clk,state,uniform1,uniform2,uniform3,uniform4,adder_r)

begin

case state is

    when s0 =>
        -- Sign extend
        adder_a <=  uniform1(9)&uniform1(9)&uniform1(9)&uniform1(8 downto 0);
        adder_b <=  uniform2(9)&uniform2(9)&uniform2(9)&uniform2(8 downto 0);

        next_state <= s1;

    when s1 =>
        adder_a <= adder_r;
        adder_b <= uniform3(9)&uniform3(9)&uniform3(9)&uniform3(8 downto 0);

        next_state <= s2;

    when s2 =>
        adder_a <= adder_r;
        adder_b <= uniform4(9)&uniform4(9)&uniform4(9)&uniform4(8 downto 0);

        next_state <= s0;

end case;
end process;

end Behavioral;

And the code of the adder for adding two 12-bit signed numbers, it has a latency of one cycle:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity adder_signed is
    Port ( clk : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR (11 downto 0);
           b : in  STD_LOGIC_VECTOR (11 downto 0);
           r : out  STD_LOGIC_VECTOR (11 downto 0));      
end adder_signed;

architecture Behavioral of adder_signed is

signal r_next : std_logic_vector(11 downto 0) := (others => '0');

begin

process(clk)

begin

if rising_edge(clk) then
    r <= r_next;
    r_next <= std_logic_vector(signed(a)+signed(b));
end if;

end process;

end Behavioral;

I wrote a testbench to write output values to a file and a mathematica notebook to test how close the numbers are to the normal distribution. Histograms were generated with "Histogram[x, 200]" command and plots with "ListPlot[x, Joined->True]", where "x" is a list of values.

500 output values of the generator.

Same amount of samples from the normal distribution.

You can see that the approximation is pretty close to the normal distribution. It's maybe a little bit fatter, but it wouldn't be noticeable without comparing it to a true normal distribution.

Histogram of the generated numbers. Does it look like a normal distribution?

Histogram of the same amount of random numbers generated from the normal distribution. Notice the different values on the axes.

As you can see from the histograms the approximation is a little bit flatter, but it comes amazingly close. Just by looking at the histogram without a normal distribution to compare it to, I would say that it is a normal distribution and that's the only thing that was important.

Appendix 1.

VHDL test bench for writing the output values into a file:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;
USE ieee.numeric_std.ALL;

ENTITY random_gaussian_test_bench IS
END random_gaussian_test_bench;

ARCHITECTURE behavior OF random_gaussian_test_bench IS

     FILE test_out_data: TEXT open WRITE_MODE is "output/gaussian.txt"; 
    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT random_gaussian
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         random : OUT  std_logic_vector(11 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';

    --Outputs
   signal random : std_logic_vector(11 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: random_gaussian PORT MAP (
          clk => clk,
          reset => reset,
          random => random
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
    variable L1 : LINE;
    variable I : integer;
   begin        
        reset <= '1';

      wait for clk_period*20;

        reset <= '0';
        wait for clk_period*30;

        for I in 0 to 1000000 loop
            wait for clk_period*3;

            write(L1, to_integer(signed(random)));
            writeline(test_out_data, L1);
        end loop;
      wait;
   end process;

END;

Progress on evolutionary circuits

2012-09-14T00:00:00+03:00

If you haven't been reading my last entries, I have been working on a program that tries to design a circuits using genetic algorithm that fulfill the requirements given by the programmer. Read this entry for an overview what the program does and how it works. In this post I will tell about my findings about which algorithms and parameters work and which don't.

Population size

Before I started writing this program I read some literature about similar experiments. For example I read some John R. Koza's books about using genetic algorithms on designing electric circuits and he used some huge population sizes. In the book Genetic Programming IV: Routine Human-Competitive Machine Intelligence population sizes that he uses are usually tens of thousands. Some of the runs use population size of 100000 which is absolutely huge. This helps to explore the whole search space and guarantees a good solution. But I have found that population sizes of this big are unnecessary and they slow down the simulation too much. I have experimented and found that population sizes of 100-2000 are often good enough and they convergence a lot of quicker to very similar solutions as the population sizes of 10000 to 20000. This is often a difference between a few hour simulation and a few days of simulation.

Crossover

I have found that the way I currently do crossovers, by cutting and pasting parts of the two circuits netlist to one new netlist often produces bad results and I have been thinking that the whole existence of crossovers might be just waste and it would be a better use of resources to just disable them. Currently on my latest files I have set the crossover probability to low value of 1% to 5%, compared to mutation probability of 70%.

The problem with crossovers is that by applying it to two similar circuits we get one circuit that has many similar parallel devices. If this circuit with parallel devices performs better than the previous circuit parallel devices will soon spread within the population and they decrease the number of devices available to the rest of the circuit. Getting rid of the unnecessary parallel device, for example a two resistor requires two lucky mutations: one of the resistors needs to be removed and others value needs to be halved. Probability of this happening is small and instead it would have been better if in the first place there would have been a mutation in the value of the resistor that would have decreased it's value. This way it wouldn't have introduced an unnecessary device and it could have been used in a better way.

Circuit encoding

I decided to encode the circuits as a simple SPICE netlists. The problem with them is that crossovers often introduce duplicate parallel devices and seem harm more than help. Also they lack clear input and output. It is equally likely that a new device will connect straight from input to output or it will connect somewhere else. This usually leads to circuits that are not very deep, meaning that input and output nodes are very close together. This makes hard to evolve circuits that need to be deep to work correctly, for example higher order filters are necessarily deep.

Koza uses binary trees and set of functions to modify it. I have not tried them myself, but they don't suffer from same problems as netlists. Crossover is more efficient because subtrees can be exchanged. It's also easier to evolve deeper circuits when whole subtrees can be moved around.

An alternatives to these two encodings would be a graph based encoding. Graphs would work by having a starting node and a list of instructions that insert devices, change the current node and instruction that does both. This way duplicating a piece of genome makes a new series connected stage that is connected to previous stage instead of duplicating devices of the previous stage. I have not tried this approach yet. It's interesting, but it has some problems. Coding it is harder than simple netlists, it is more computationally intensive because the circuit needs to be converted to netlist for simulation and handling devices with more than two connections(e.g. Transistors) will be harder. Hopefully it will be worth it and evolving deeper circuits will become easier.

Lowpass filter encoded with graph encoding.

Same lowpass filter, but with a crossover that duplicated the instructions. Instead of parallel devices, the circuit now has a second stage.

Scoring

One of the most important things I have found that improve the quality of evolved circuits is that instead of keeping the constraint functions scores constant I ramp up the scoring weights over many generations and increase the strictness of constraints. For example when evolving an inverter I had a problem where my constraints for the current use were so strict that the program decided that it's better to not make anything to keep current use low instead of trying to make an inverter and use current. Ramping constraint scores solves this problem by allowing the program first make circuits that use lots of current, but work like they should and after some working circuits are found concentrate on fulfilling the constraints. In the inverter example this leads to very current efficient inverters that work like they should.

Summary

Since announcing this project I have made many improvements. Current and used power can be measured and controlled. Better scoring and improvements in scoring algorithm. New mutations that can change the output node and other mutation that changes a value of a device only a little amount, probably other mutations that I have forgotten already. Device can have an arbitrary cost(price, amount of area used...) that is added to the circuits score. The biggest improvement might be the gradual ramping of constraint scores that generate higher quality solutions. I have also replaced the unmaintainable way of writing the circuits straight to the programs source code with separate configuration files that are easier to write and maintain.

I have also added more options. For example it is now possible to not use the default scoring functions, but instead to write your own function that takes the simulation output and returns the score of the circuit.

I have also since replaced Python with PyPy. It uses much less memory, usually two to ten times less. With extremely big populations memory saving are even bigger. There might be something weird in the Python reference counting that keeps useless simulation results in memory instead of freeing them. I haven't investigated it much, because PyPy works so much better. Only problem with PyPy is that matplotlib isn't supported. Currently I run matplotlib as a subprocess, but PyPy team is working on supporting it and I hope that soon I can do the plotting also with PyPy.

In-place sparse matrix conversion algorithm

2012-08-15T00:00:00+03:00

I have been writing a sparse matrix library for few weeks and for it I needed a algorithm for converting from coordinate list form(COO) matrix to compressed sparse column form(CSC). All of the algorithms that I found allocated space for the CSC matrix and freed the COO matrix after building the CSC matrix. This is inefficient when I know that I don't need the coordinate list matrix after building the CSC matrix. So I decided to make an algorithm that can convert the matrix in-place.

Same matrix in COO and CSC formats. COO formats order is arbitrary. This time the Column array in CSC is the same length as number of non-zero entries, but in general its length is columns in matrix + 1, or one less if you leave the last optional element out.

Above is example of same matrix in COO and CSC formats. Note that order in COO format is arbitrary and it can have duplicate elements. Traditionally values of the duplicate entries are summed together, because this

If you look at the above CSC and COO formats of the example matrix, it should be clear that CSC formats Value and Row arrays are just sorted COO formats Row and Value arrays. Only problem is the Column array but it can be built easily from the sorted Column array. We just need to compare current element to previous element and if they are not equal set the next unset element to be the current loop iteration.

Matrix->Col[0] = 0;
t = 0;
p = 1;
for(i = 1; i < Matrix->Entries; i++) {
    t1 = Matrix->Col[i];
    if (Matrix->Col[i]!=t)
        Matrix->Col[p++]=i;
    t = t1;
}
Matrix->Col[p] = i;

Because we want to sort the arrays in-place first choice for the sorting algorithm is Quicksort. I know that it really requires O(log n) of space in the stack because of the recursion, but in reality it's less than 1kB even for a several gigabyte big matrices so we don't really need to worry about it. We need to sort both Row and Col arrays, such that Row is sorted first and then Col, but there is no need to make two passes as we can just define our comparison such that the Quicksort algorithm sorts both arrays at the same time. Below is the full algorithm and the same example matrix as above.

#include <stdio.h>

#define comp(_a,_b,_x,_p) (_a[_x]!=_a[_p] ? _a[_x]-_a[_p] : _b[_x]-_b[_p])

typedef struct matrix {
    int *Row;
    int *Col;
    double *Elements;
    int Entries;
} matrix;

void COOtoCSC(matrix*);
static void q_sort(matrix *Matrix, int lo, int hi);

void COOtoCSC(matrix *Matrix) {
    int i, t1, t, p, k;

    /*  Sort by first Col and then Row */
    q_sort(Matrix, 0, Matrix->Entries-1);

    k = 0;
    /*  Remove duplicates */
    for( i = 1; i < Matrix->Entries; i++) {
        if ( (Matrix->Row[k] != Matrix->Row[i]) || (Matrix->Col[k] != Matrix->Col[i]) ){
            k++;
            Matrix->Row[k] = Matrix->Row[i];
            Matrix->Col[k] = Matrix->Col[i];
            Matrix->Elements[k] = Matrix->Elements[i];
        } else {
            Matrix->Elements[k] += Matrix->Elements[i];
        }
    }
    Matrix->Entries = k+1;
    Matrix->Col[0] = 0;
    t = 0;
    p = 1;

    /*  Build CSC column pointers in the Col array */
    for(i = 1; i < Matrix->Entries; i++) {
        t1 = Matrix->Col[i];
        if (Matrix->Col[i]!=t)
            Matrix->Col[p++]=i;
        t = t1;
    }
    Matrix->Col[p] = i;
    return;
}

static void q_sort(matrix *Matrix, int lo, int hi ) {
    int h, l, p, p1, p2, t;
    double p3, td;

    if(lo>=hi)
      return;

    l = lo;
    h = hi;
    p = hi;;
    p1 = Matrix->Col[p];
    p2 = Matrix->Row[p];
    p3 = Matrix->Elements[p];

    do {
      while ((l < h) && (comp(Matrix->Col,Matrix->Row,l,p)<=0))
          l = l+1;
      while ((h > l) && (comp(Matrix->Col,Matrix->Row,h,p)>=0))
          h = h-1;
      if (l < h) {
          t = Matrix->Col[l];
          Matrix->Col[l] = Matrix->Col[h];
          Matrix->Col[h] = t;

          t = Matrix->Row[l];
          Matrix->Row[l] = Matrix->Row[h];
          Matrix->Row[h] = t;

          td = Matrix->Elements[l];
          Matrix->Elements[l] = Matrix->Elements[h];
          Matrix->Elements[h] = td;

      }
    } while (l < h);

    Matrix->Col[p] = Matrix->Col[l];
    Matrix->Col[l] = p1;

    Matrix->Row[p] = Matrix->Row[l];
    Matrix->Row[l] = p2;

    Matrix->Elements[p] = Matrix->Elements[l];
    Matrix->Elements[l] = p3;

    /* Sort smaller array first for less stack usage */
    if (l-lo

Better evolved BJT inverter

2012-07-20T00:00:00+03:00

In my first post about my evolutionary circuits project I wrote about an evolved BJT inverter. I have since that post written some new features in the program. Now it can measure the current taken from logic input and the power supply, so the last best solution where the transistors would be fired shouldn't be possible anymore. I also made possible for the program to decide where the transition from high to low input should be. Last feature that I just finished a few minutes ago was constraints on the measured values. If measurements don't fill the constraints the circuit gets ranked very poorly and has a low probability to be chosen to the next generation. Reason I added the constraints was because I tried to evolve a BJT inverter before adding them and the program got stuck on the minimum where the best inverters low to high transition was very fast, but other transition didn't work at all.

DC sweep of the broken inverter. Blue is the goal and green is the circuits output. With the 5V input output is 2.1V, which is above the transition voltage. If this inverter would drive another inverter the second inverter would output 1.5V which is the low voltage, but output should be 5V, same as input, because it was inverted twice.

High to low transition is fast...

...But low to high transition doesn't work

So the constraints were necessary to guarantee that the program wouldn't get stuck on broken solutions. After implementing them I tried to evolve a BJT inverter again. Allowed components were: resistors, capacitors, 2N3904 and 2N3906 transistors. To avoid unreasonable big capacitors I limited the maximum capacitor value to 100pF. Picofarad capacitors were chosen because they are reasonable size for integrated circuits. Maximum number of components was 8 and population size was set to 4000 circuits. I also tried to model the finite impedance of the input with 50 series resistance and to avoid circuits that wouldn't work with load I fixed a 10kΩ load resistor to the output.

This time I measured: current taken from logic input, current taken from the 5V power supply, input DC sweep from 0V to 5V, high to low and low to high transitions. Because measurements from SPICE are in basic SI units, the program will rank 1A average decrease in current usage same as 1V average decrease in transfer curve, to get the program appreciate current more the current scores were multiplied with one thousand so that 1mA decrease in current would equal 1V decrease in the transfer curve.

Previously I arbitrarily chose the transition voltage to be 2.5V, but since then I have improved the program and now it's possible for it to decide where the optimal transition is. Ordinary RTL or TTL inverters don't switch exactly at the half of power supply value either and it's very likely that the evolved inverter would perform better if it wasn't artificially limited to switch at 2.5V.

Constraints were placed on the transient simulation values and DC current usage. After the transition the inverter was required to settle to 0.2V below or above the transition voltage depending on the which transition it was. This way the broken inverters like on the above hopefully wouldn't be possible anymore.

This time I ran the simulation a lot longer than in my first post. I started it in the morning before going to the work and stopped it after coming home. Total running time was 12.5 hours. Below are the animated gifs of the measurements of the best circuits of each generation, currents aren't plotted because they were so close to zero that they all looked just like a straight line. But if you still want to look at some straight lines here's input current and here is current taken from the power supply.

DC sweep. Blue line is the goal and green is the circuits output.

High to low transition. Scale of x-axis is 50ns/division.

Low to high transition.

Schematic of the final circuit

Static current usage

Voltage supply V2 is the logic input and V1 is 5V power supply. This is very neat looking circuit, looks almost like it could have been designed by a human. It doesn't have any unconnected or unneeded components, even the 27pF capacitor is needed(It improves the propagation delay). Especially the input stage is interesting with the 3 parallel PNP transistors. Connecting transistors in parallel improves their frequency response and current handling capacity. If this is built from discrete components connecting transistors in parallel might be problematic because the transistor might not be matched that well. But it shouldn't be a too much trouble because single transistors could handle all the current going through the three of them. If this was an integrated circuit the 3 individual transistors could be combined to one three times bigger transistor.

If you look at the above transient responses it looks like it's rise and fall time is really fast. In SPICE simulation both rise and fall time are about 1.3ns. If you compare these to the ordinary RTL inverter built with 2N3904 transistor and using 15k base resistors it has a fall time of 80ns and a rise time of almost 2µs(=2000ns). RTL inverters maximum static current usage is 1.5mA when input is at 5V. The evolved inverters maximum current use is just 660µA when the input is at 4.5V. Downside of course is that the evolved inverter uses more components than the RTL inverter.

Schematic of RTL inverter

Schematic of one TTL inverter. This is commonly called a TTL inverter with a totem pole output stage.

But RTL is old technology and not in use anymore, but other bjt based logic family that is still used is TTL. When built with 2N3904 transistors the TTl inverters maximum static current consumption is 36mA. TTl inverter is quicker than the RTL inverter. It has a fall time of 1.8ns and a rise time of 1.6µs. The reason both RTL and TTL inverters have slow rise time is because after being in saturation it takes time to remove the stored charge from the base and get transistor to the cutoff state. Evolved circuit takes care of this by dumping huge current spike through the base of Q5. When the input changes state from 5V to 0V, it creates a current through the capacitor. Part of the current goes to logic input and part of it goes through the 4 PNP transistors at the input to the base of Q5. Voltage at the base quickly decreases to -2V. Size of the current spike depends on the fall time of the logic input. Quicker it falls the bigger the spike and faster the outputs transition is. It should be noted that even tough the maximum current in the evolved circuit is bigger than in TTL inverter its duration is very short and the total amount of energy required to change output is smaller in the evolved circuit.

Current taken from the power supply. Input changes at 10ns. And it falls in 1ns. With 0.1ns fall time maximum current is 77mA. 2N3906 can handle 200mA of continuous current and even higher amounts for short time so this isn't enough to break it. 24mA of this goes through the Q5 and rest of it goes to logic input, which might be a problem for the circuit driving the inverter.

I also built the circuit to make sure that it works when built with real components. Unfortunately I have only single probe on my oscilloscope so I can't measure the rise and fall times and even if I had the second probe it would be a waste of time trying to measure this when built on a breadboard because breadboard has big parasitic capacitances which would mess up the capacitances near the 10pF capacitor. So this should be built on either IC or using the Dead bug style. But I could measure the static current usage and the input DC sweep:

Built with real transistors.

Current when the input is at 0V. 325µA. You can also see the LED at the output light up.

Current when the input is at 5V. 276µA. 0V on the output as you can see from the LED.

Simulated with LED and 10k resistor at the output.

DC sweep with triangle wave at the input. 0V is at the left and 5V at the right. Transition voltage is about 4.5V as simulated.

Current is near the simulated values but not quite there. 0V input current is very near the simulated value but the 5V input for some reason is much less. No idea whats going on here. Tolerances on the transistors or resistors?

Could this circuit be used in a production? Maybe, even though it has some problems it's faster than the ordinary TTL inverter. It has a few problems with the big resistor values, small 27pF capacitor and current spikes in the logic input and the power supply. It also has a few volts of overshoot on the output voltage on high switching frequencies. Replacing the Megaohm resistors with smaller values helps but increases current usage.

Overshoot on the output. 33MHz switching frequency. Faster than the TTL inverter is capable of(when using 2N3904 transistors, it can go higher with faster transistors. Same with this circuit).

When fast rise and fall time is important this might be useful circuit, but before using it anywhere it might need some hand designing to fix the overshoot and current spikes. Overall it is a big increase in the quality compared to the previous inverter circuits.

If you want to try it yourself download the code from github and run the "inverter.py" file. That version also has scoring for the transient current usage. The program works on Linux and might or might not work on Windows.

Metastable transistor circuit

2012-07-13T00:00:00+03:00

In my previous post I wrote about a circuit that would change it's output depending on what was the spice simulations DC sweep range. Today I investigated the circuit a little and I was able to remove lots of components that didn't affect the bug and this is the resulting circuit:

Schematic

Spice simulation results of the changed circuit:

DC sweep from 0V to 10V

DC sweep from 5V to 10V

The next step was to build this circuit using real transistor and measure what the real output is.

Circuit built on the breadboard

First I tried to power the circuit from 9V battery and the measured output was 7.5V(The reason I use batteries is because I don't have a proper power supply, I have the components to make one using LM317 but I haven't found time yet). Spice simulated that output voltage would be 8.5V(or 50µV), but the 9V battery I'm using isn't exactly new and adding 300Ω resistor to series with the voltage source to model the internal resistance of the battery gives output of 7.5V at 9V input. I also tried to get the output to stay at the 0V and I found out that if I power the circuit with even emptier 9V battery that gives only 4.7V at the output and touch lightly with a grounded wire to the base of Q2, output voltage stays near 0V for few seconds and then rises quickly back to 4.7V. I couldn't really capture this in a picture so I took a video instead:

Your browser does not support the video tag.

So in the end Spice was sort of correct. The circuit does have one stable state when the output is almost supply voltage and other metastable state where output is near 0V. The 0V state might be stable in the simulation, but small differences in the transistors or inaccurate models in the simulation might make this state only metastable.

Building an evolved voltage reference

2012-07-12T00:00:00+03:00

I've been playing with the electronic circuit genetic algorithm design program. I have tried to make some stable bandgap voltage references, so far results have been promising, but not very good. None of the resulting circuits could be used in a production, except if you don't care much about the temperature stability.

One circuit that seemed good when it was evolved was this one(No circuit diagram because I'm lazy):

.model 2N3906  PNP(Is=455.9E-18 Xti=3 Eg=1.11 Vaf=33.6 Bf=204.7 Ise=7.558f
+               Ne=1.536 Ikf=.3287 Nk=.9957 Xtb=1.5 Var=100 Br=3.72
+               Isc=529.3E-18 Nc=15.51 Ikr=11.1 Rc=.8508 Cjc=10.13p Mjc=.6993
+               Vjc=1.006 Fc=.5 Cje=10.39p Mje=.6931 Vje=.9937 Tr=10n Tf=181.2p
+               Itf=4.881m Xtf=.7939 Vtf=10 Rb=10)
.model 2N3904   NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259
+               Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1
+               Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75
+               Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10)
Vin n1 0
rload n2 0 100k
R39826856 n4 n11 1709.1717943
R52792856 n2 n10 2507.84316862
Q155540048 n0 n11 n5 2N3906
Q21597538600 n8 n3 n10 2N3904
R51398488 n0 n11 25282.9648097
R52736296 n10 n2 3272.12493658
R58783432 n7 n5 23812.5332944
R52713520 n4 n6 116372.392136
Q168167800 n1 n6 n3 2N3906
R57551328 n10 n3 821383.334394
Q158216032 n10 0 n10 2N3906
Q259752248 n2 n5 n1 2N3904
Q170112896 n10 n7 n2 2N3906
Q279097800 n3 n7 n11 2N3904
Q21325009232 0 n8 n4 2N3904
R39671064 n6 n11 30496.553302
R47819448 n1 n0 22223.2407018
R42659568 n1 n0 401.01058083

When input is swept from 4V to 10V, with step of 0.1V. This is the output voltage:

Spice command: dc Vin 4 10 0.1

Looks good, but when output is swept from 0V to 10V this is the result:

Spice command: dc Vin 0 10 0.1

Note the y-axis values. After changing only the range of the simulation spice returns completely different results for the whole range. I investigated this a little and when the DC sweep starting value is lower than 3.8441V spice returns the almost zero output value. If starting value is 3.8442V this is the output:

Spice command: dc Vin 3.8442 11 0.1

For the starting values 3.8443V and higher spice returns same results as in the first picture. I don't know which output is really correct and I don't really care that much as the circuit wasn't that good anyway, but if you decide to build this circuit let me know the results.

New bandgap voltage reference

For the next simulation I changed evolution's goals to avoid spice bugs. I varied the dc sweep starting and ending values a small amount for every spice simulation. I also learned from my last post and added input current measurements, more measurements with different load resistances and measurements with different temperatures. I also changed goals so that I didn't check what value output voltage was, but only scored circuits for the stability of the output voltage and let the evolution to decide what is a easy to build voltage reference, but because permanent 0V on the output would also be stable I added a check that output voltage is higher than 1V. I also added a transient simulation that simulates a circuits response to 10V step in input voltage. Transient response isn't that important, but its reason is avoiding bugs. Transient simulation is harder than dc sweep and if spice doesn't know how to simulate a transient response it sure doesn't know to simulate the dc sweep. And if you're wondering why these changes aren't in the github, it's because I just hard coded everything and it can't be currently used to simulate anything else. I will be adding these changes too, but I need to make sure first that the program still works.

I decided to abort the simulation after 30 minutes to avoid overfitting and because the resulting simulations looked good.

Generation 50. Schematic as the program designed it. Output is on the collector of Q3

Unnecessary parts removed. I later realized that R3 can also be removed. R2 is the load resistor

Previous circuit redrawn and R3 removed. Labels changed.

Simulation results, output voltage is 1.4V, which is about 2*Vbe of a bjt transistor.

Rload stepped from 1k to 10k with 1k step. Output begins to fall if load is less than 1k.

Zoomed view of previous plot

The simulations look very promising, especially the constant voltage despite the load resistance, which I had problems with last time. Input current is also small and transistors should not break. Because the simulations looked so good I decided to build this circuit and test it's output.

Built with real components:

I changed the 800 Ohm resistors to 1k Ohms because I didn't have 800 Ohms resistors. Load resistor is 10k Ohms

Measured output: 1.362V at room temperature(20° C) when powered from 9V battery, Spice simulated 1.42V.

I measured the temperature coefficient by placing the circuit in the freezer for few hours.

Measured output: 1.47V at about -20°C again powered from 9V battery. Taking pictures and using the multimeter same time is hard.

Temperature coefficient is about 3mV/°C, not very good as voltage reference but might be okay for some applications where temperature doesn't change that much.

DC sweep, input is 0V to 10V triangle wave, 0.5V/div

Zoomed, 0.2V/div, there was some DC offset in the input triangle wave so the bottom isn't actually ground

As you can see above the circuit really works as a voltage reference. I think it has a very good performance considering that it uses only three transistors, at least it's better than anything I could have designed using three transistors.

Error due to the input voltage is about 20mV/V.

10V step input response, 2µs/div, 0.5V/div

Transient behaviour is good. Output voltage rises very quickly, quicker than I can measure with my 60Mhz oscilloscope, but it falls slowly.

Output voltage was little off from the simulated value, but transient response and dc sweep looked very much like in the simulation. I tried to change some of the transistors, but it didn't change output voltage much. Overall considering that the circuit uses only three transistors and the computer made it in 30 minutes it's behaviour is good.

Evolutionary algorithms and analog electronic circuits

2012-07-07T00:00:00+03:00

I've been working for a while on a program that automatically generates analog electronic circuits using evolutionary algorithms. It's still very much a work in progress, but I've used it to generate some useful circuits. Current workings of the program is as follows:

Programmer decides a goal function, possible constraints, simulation type(AC, DC, Transient), number of nodes and types and values of the components available. Possibly tweaks genetic algorithm parameters, such as: population size, mutation probability etc...
First generation of circuits is randomly generated and they are simulated in SPICE(I use ngspice).
Outputs of the simulations are ranked against the goal function and good performers are mutated and added to the new generation of circuits.
This is repeated until a good enough circuit is found.

For example I have used it to find inverter circuits, bandgap references and rising edge detectors.

BJT Inverter, with 4 components

First circuit that I evolved was a inverter using bjt transistors. Options were:

Maximum of 4 components.
Allowed components: 2N3904 and 2N3906 transistors and resistors with values of 0.1 to 10M Ohms.
I also provided one 5V power supply.
SPICE simulation was DC sweep from 0 to 5V and the goal was transition on 2.5V. Rise and fall times were not tested.

Below is an animated gif of the responses of the best circuits:

As you can see the response improved quickly and last big breakthrough was in generation 78 and it took only 9 minutes to get there. Generation 2049 was reached 6.5 hours after starting.Currently the program isn't multithreaded and circuits are tested one at a time. Simulating more circuits at the same time should improve the simulation time linearly depending on number of available processor cores.

The best circuit in generation 70

The best circuit in generation 78

If you compare the circuits in the generations 70 and 78 you can see that the breakthrough was in reconnecting Q2, it's base was connected to the base of Q3 and collector was connected to the input. Q4 was also removed but it didn't really do anything because it was permanently in the cutoff state. There's no more big changes and rest of the time was spent on trying to find a suitable fourth component. In the final circuit, generation 2049, fourth component was resistor and circuit greatly resembles a CMOS inverter.

Circuit in generation 2049(If you are wondering what Q3 does, it doesn't really do anything.)

CMOS inverter

This is looks like it might work, but if we plot currents taken from input and current going to ground. We see that maximum current taken from the power supply is 200mA. This is horribly inefficient and it's probably more than the transistors can handle.

Currents at the collectors of the transistors

And if we look at the base current of Q1 maximum current is 210mA when input is at 5V. This is too much for 2N3904 transistor and real transistor would probably break.

Base current of Q1 as a function of input voltage

It makes sense that if power consumption of the circuit isn't tested it will evolve so that it doesn't care about power consumption. It's easier to use lots of power than to use a little of it.

One problem is also that SPICE is happy to simulate that current through transistor is 100A, even if it clear that real component wouldn't be able to withstand that much current. To make this program useful it's probably necessary to add checks that power used by components is reasonable.

Bandgap reference

Another circuit that I evolved is a bandgap reference. Goal was to generate stable 2.5V output voltage when the supply voltage varied from 4V to 10V. SPICE can also simulate temperature so added two input DC sweep with temperatures of 27 and 60 degrees Celsius. This time number of components was restricted to eight and components available were same as in the inverter evolution(2N3904 and 2N3906 transistors and resistors).

Below are animated gifs of output voltages on different temperatures as a function of input voltage, I also added the current score to the plot:

The final bandgap circuit

Output voltage as a function of input voltage, temperature: 27 degrees

Because converting SPICE netlist to schematic must be done by hand and is time consuming I'm only giving a schematic of the final circuit.

As you can see on the output sweep that the reference isn't that accurate and this circuit also has a power consumption problem. R2 is only 20 Ohms and it takes lots of current from the power supply, when supply voltage is high. If R2 is changed to a bigger value output voltage drops slightly. I exchanged it to a 10k resistor and output voltage drops to 1.3V and current taken from the supply is only 0.5mA when input voltage is 4V and 1.4mA when voltage is 10V. This starts to be a reasonable current considering that transistors used are discrete components. If this was an integrated circuit it would be still a too big current.

Other problem that this circuit has is that it's output voltage drops when the output is loaded.

Output voltage as a function of input voltage with different load resistances

In the above picture output voltage is swept and load resistance is stepped from 1k to 100k with a step of 10k. With 100k load 1.3V reference becomes 1.25V reference and output voltage decreases quickly when load resistance is decreased with a 1k load reference doesn't work correctly anymore. This plot is made with R2 changed to 10k.

With 100k load output voltage is 1.39V when input voltage is 10V and 1.29V when input voltage is 4V. Output voltage rises about 1.6mV per 1V increase in input voltage.

If temperature is 60 degrees Celsius. Output voltage is 1.18V when input is 4V and 1.29V when input is 10V. Temperature dependency is about -3mV per degree Celsius. Not very good as a reference but considering that this was generated automatically I think it's a success, even tough it's output voltage isn't 2.5V as was required. Allowing more components would have probably generated a more accurate reference.

I would make this circuit using real components and test how it performs in real life, but I don't have enough transistors.

If you are interested in the code it's available at my github account, but I must warn you that it's not easy to use and requires a Linux OS and ngspice for simulating circuits, but I would still appreciate any contributions.

I think this looks promising and if I can implement automatic check for used power and that currents and voltages are reasonable for real components, it might be actually useful.

Redefining the number 2 in Python

2012-06-29T00:00:00+03:00

In Python it's possible to redefine some builtin values that shouldn't really be changed. For example True and False can be changed in Python versions 2.7 and lower. This is fixed in Python 3 and assignment to True or False raises: "SyntaxError: assigment to keyword" but it works on Python 2.7:

Python 2.7.3 (default, Apr 20 2012, 22:39:59) 
[GCC 4.6.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> True,False = False,True #Exchange True and False
>>> id(True)
9071696
>>> id(False)
9071664
>>> 1==1
True
>>> id(1==1) #This returns the id of False, but interpreter printed True last line
9071664 
>>> (1==1)==True #True doesn't equal True
False

Because of some internal Python workings only Trues and Falses that are written by the programmer are exchanged. Trues and Falses returned by Python are exchanged but are printed as not exchanged, as can be seen on the program above.

True and False aren't the only builtin values that can be changed, because CPython caches small integers we can change values of the integers in the cache.

In Python 2.7 and lower Python integers are represented in the C code as PyIntObject that has following definition:

typedef struct {
    PyObject_HEAD
    long ob_ival;
} PyIntObject;

PyObject_HEAD is a C macro that by default expands as:

Py_ssize_t ob_refcnt;
PyTypeObject *ob_type;

ob_refcnt is the reference count and ob_type is a pointer to a structure that is used describe Python built-in types.

Using the "ctypes" module we can change ob_ival field that stores the value of the integer. We can get the address of the integer with id() function and we know that because of the internal representation of the Python integer, ob_ivals offset from the start of the struct is sizeof(size_t)+sizeof(void *). Following code changes the ob_ival value of the cached integer 2 to 3:

import ctypes

value = 2
ob_ival_offset = ctypes.sizeof(ctypes.c_size_t) + ctypes.sizeof(ctypes.c_voidp)
ob_ival = ctypes.c_int.from_address(id(value)+ob_ival_offset)
ob_ival.value = 3
print 1+1

Because of the integer cache every time Python thinks that it's using the integer 2 it's actually using the value 3. In Python 2.7 this program prints 3 and crashes. Running this in the interactive shell works, but trying to use it afterwards might lead to interesting behavior if it needs the value 2.

This code doesn't work in Python 3.0 or newer versions, because in Python 3.0 int and long types were combined in the one single type and this changed the PyIntObject struct.

First Post

2012-06-25T00:00:00+03:00

This is a blog about electronics, computers and mathematics. I'm thinking about writing for example: VHDL, FPGAs, general electronics, LaTeX, programming, pitfalls in Python and lots of other stuff. Recently I have written a program that uses evolutionary algorithms to autonomously design analog electrical circuits. I have had some success with it and I think I'm going to write a post or two about it when I have a time. Another recent project that I'm going to write about in the future is implementation of the cordic algorithm on a FPGA.

As you can see this blog is powered by Pelican. Theme is currently default theme of the Pelican. I'll tweak it when I have time, but I'm going to concentrate on the content at the moment.

Variable	Explanation	Value
\(P_t\)	Transmitted power	30 dBm
\(G\)	Antenna gain	10 dBi
\(\lambda\)	Wavelength	5.2 cm
\(\delta x \delta y\)	Image pixel resolution	0.3 x 0.3 m
\(T\)	Receiver temperature	290 K
\(t_s\)	Pulse length	200 µs
\(n\)	Number of pulses in image	10000
\(F\)	Receiver noise figure	6 dB
\(\alpha\)	Grazing angle	30 deg

Antenna pair	Traveled distance
TX2-RX1	\(2r_{tx1} -d\sin\theta\)
TX2-RX2	\(2r_{tx1}\)
TX1-RX1	\(2r_{tx1} + d\sin\theta\)
TX1-RX2	\(2r_{tx1} + 2d\sin\theta\)

Variable	Explanation	Value
\(V_\text{ref}\)	ADC maximum peak-to-peak voltage	2 V
\(G_\text{IF}\)	IF amplifier gain	20 dB
\(G_\text{LNA}\)	LNA gain	20 dB
\(G_\text{mixer}\)	Mixer power gain	0 dB
\(k\)	Boltzmann constant	1.38064852×10^-23 m² kg s^-2 K^-1
\(T\)	Noise temperature	290 K
\(Z_\text{load}\)	Mixer output impedance	200 Ω
\(F\)	Receiver noise figure	6 dB
\(t_s\)	Sweep length	1 ms